Flat panel display device and method for manufacturing the same

• US 6,559,477 B2
• Filed: 09/28/2001
• Issued: 05/06/2003
• Est. Priority Date: 09/29/2000
• Status: Expired due to Term

• Current Assignee: Japan Display Central Incorporated (Japan Display Incorporated)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yoshihashi, Hideo, Tada, Norio
• Primary Examiner(s): Pham, Long
• Application Number:
  US09/964,403
• Publication Number:
  US 20020039814A1
• Time in Patent Office: 585 Days
• Field of Search: 438/149, 438/151, 438/155, 438/164, 257/59, 257/69, 257/72, 257/68
• US Class Current: 257/59
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors

Abstract

A flat panel display device comprising a thin film semiconductor switching element formed on a surface of a substrate, a display electrode connected with the switching element, a semiconductor layer for auxiliary capacity which is electrically connected with the display electrode, a dielectric layer formed on a surface of the semiconductor layer for auxiliary capacity, and a metal layer formed on a surface of the dielectric layer, wherein the auxiliary capacity is constituted by the semiconductor layer for auxiliary capacity, the dielectric layer, and the metal layer, and the semiconductor layer for auxiliary capacity is implanted all over the surface thereof with a high concentration of impurity ion.

Claims

1. A flat panel display device comprising:

a thin film semiconductor switching element formed on a surface of a substrate;

a display electrode connected with said switching element;

a semiconductor layer for auxiliary capacity which is electrically connected with said display electrode;

a dielectric layer formed on a surface of said semiconductor layer for auxiliary capacity; and

a metal layer formed on a surface of said dielectric layer;

wherein the auxiliary capacity is constituted by the semiconductor layer for auxiliary capacity, the dielectric layer, and the metal layer; and

said switching element includes a channel region, and a semiconductor layer having source and drain regions disposed to sandwich the channel region therebetween and implanted respectively with an n-type or p-type impurity ion, the impurity ion having the same as the impurity ion concentration being implanted into the source/drain regions is implanted into the semiconductor layer for auxiliary capacity in the same step, a surface concentration of the n-type or p-type impurity ion is in the range of 3.2×

10¹⁹ to 2.0×

10²⁰ atoms/cm³.

2. The flat panel display device according to claim 1, wherein the number of defects per unit volume which exists in the gate insulating film of switching element and in the semiconductor layer is not more than 6.91×

10¹⁸/cm³.

3. The flat panel display device according to claim 1, wherein said impurity ion is mainly formed of phosphorus.

4. The flat panel display device according to claim 1, wherein said substrate includes a driving circuit sending a signal to said display electrode, and said driving circuit includes a thin film transistor formed in the same step as that forming said switching element.

5. A flat panel display device comprising:

a thin film semiconductor switching element, and a thin film semiconductor element for driving circuit, both being formed on a surface of a substrate;

a display electrode connected with said switching element;

a semiconductor layer for auxiliary capacity which is electrically connected with said display electrode;

a dielectric layer formed on a surface of said semiconductor layer for auxiliary capacity; and

a metal layer formed on a surface of said dielectric layer;

wherein the auxiliary capacity is constituted by said semiconductor layer for auxiliary capacity, said dielectric layer, and said metal layer;

said thin film semiconductor element for driving circuit is provided with a semiconductor layer having a channel region bearing thereon a gate insulating film, and source/drain regions sandwiching said gate insulating film, each of source/drain regions being implanted with a predetermined concentration of impurity ions; and

said gate insulating film of said thin film semiconductor element for driving circuit contains not more than 1.1×

10¹³/cm² in the number of defects per unit area.

6. The flat panel display device according to claim 5, wherein the concentration of an n-type or p-type impurity ion in the semiconductor layer for auxiliary capacity is in the range of 3.2×

10¹⁹ to 2×

10²⁰ atoms/cm³.

7. A flat panel display device comprising:

a thin film semiconductor switching element formed on a surface of a substrate;

a display electrode connected with said switching element;

a semiconductor layer for auxiliary capacity which is electrically connected with said display electrode;

a dielectric layer formed on a surface of said semiconductor layer for auxiliary capacity; and

a metal layer formed on a surface of said dielectric layer;

wherein the auxiliary capacity is constituted by the semiconductor layer for auxiliary capacity, the dielectric layer, and the metal layer; and

said switching element includes a channel region, and a semiconductor layer having source and drain regions disposed to sandwich the channel region therebetween and implanted respectively with an n-type or p-type impurity ion, the impurity ion having the same as the impurity ion concentration being implanted into the source/drain regions is implanted into the semiconductor layer for auxiliary capacity in the same step, a carrier concentration thereof is 1.6×

10¹⁹ atoms/cm³ or more.