Regenerative signal level converter

• US 6,559,685 B2
• Filed: 04/16/2001
• Issued: 05/06/2003
• Est. Priority Date: 04/21/2000
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Green, Michael M.
• Primary Examiner(s): TON, MY TRANG
• Application Number:
  US09/836,742
• Publication Number:
  US 20010033186A1
• Time in Patent Office: 750 Days
• Field of Search: 327/51, 327/52, 327/55-57, 327/63-65, 327/69, 327/70, 327/72, 327/76-82, 327/85, 327/89, 327/90, 365/205, 365/207
• US Class Current: 327/57
• CPC Class Codes: H03K 3/35613 the input circuit having a differential configuration

Abstract

Method and circuitry for converting a differential logic signal to a single-ended logic signal that minimize delay. In specific embodiments differential logic signals of the type employed in, for example, current-controlled complementary metal-oxide-semiconductor (C³MOS) logic are converted to single-ended rail-to-rail CMOS logic levels using the regenerative action of a

Claims

1. A complementary metal-oxide-semiconductor (CMOS) circuit for converting a differential logic signal to a single-ended logic signal, comprising:

a differential input stage coupled to receive the differential logic signal and configured to steer current into a first output branch or a second output branch in response to the differential logic signal;

a first output transistor having a gate terminal coupled to the first output branch;

a second output transistor having a gate terminal coupled to the second output branch; and

a CMOS latch coupled between the first output transistor and the second output transistor.

2. The CMOS circuit of claim 1 wherein the CMOS latch comprises:

a first node coupled to the first output transistor;

a second node coupled to the second output transistor;

a first inverter having an input coupled to the first node and an output coupled to the second node; and

a second inverter having an input coupled to the second node and an output coupled to the first node.

3. The CMOS circuit of claim 2 wherein when the differential logic signal signals a first logic state, the differential input stage activates the first output transistor, and when the differential logic signal signals a second logic state, the differential input stage activates the second output transistor.

4. The CMOS circuit of claim 3 wherein the first output transistor is configured such that when it is activated it applies a self-regulating current pulse to the first node.

5. The CMOS circuit of claim 4 wherein the second output transistor is configured such that when it is activated it applies a self-regulating current pulse to the second node.

6. The CMOS circuit of claim 1 wherein the differential input stage comprises:

first and second differential input transistors coupled to receive the differential logic signal;

first and second load devices respectively coupling the first and second differential input transistors to a power supply node; and

a current source coupled to a common-source terminal of the first and second differential input transistors.

7. The CMOS circuit of claim 6 wherein the first output transistor comprises the gate terminal coupled to the first differential input transistor, a first current-carrying terminal coupled to the power supply node and a second current carrying terminal coupled to a first node of the CMOS latch.

8. The CMOS circuit of claim 7 wherein the second output transistor comprises the gate terminal coupled to the second differential input transistor, a first current-carrying terminal coupled to the power supply node and a second current carrying terminal coupled to a second node of the CMOS latch.

9. The CMOS circuit of claim 8 wherein the first and second differential input transistors comprise n-channel transistors, the first and second load devices comprise p-channel transistors, the current-source comprises an n-channel transistor, and the first and second output transistors comprise p-channel transistors.

10. The CMOS circuit of claim 6 wherein the first and second load devices comprise transistors.

11. The CMOS circuit of claim 6 wherein the first and second load devices comprise resistors.

12. A complementary metal-oxide-semiconductor (CMOS) circuit comprising:

a first circuit implemented in current-controlled CMOS (C³MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to a differential input signal;

a differential signal to single-ended signal converter coupled to the first circuit, the converter having a CMOS latch that is configured to switch states in response to a self-regulating current pulse that is generated in response to the differential input signal, thereby converting the differential signal from the first circuit to a single-ended CMOS logic signal; and

a second circuit coupled to the converter to receive the single-ended CMOS logic signal and implemented in standard CMOS logic wherein substantially zero static current is dissipated.

13. The CMOS circuit of claim 12 wherein the differential signal to single-ended signal converter further comprises:

a differential pair input structure having a first branch with a first input transistor coupled to a first load device, and a second branch with a second input transistor coupled to a second load device, and a current source coupled to the first and second input transistors;

a first output transistor coupled to the first branch and to a first node of the CMOS latch; and

a second output transistor coupled to the second branch and to a second node of the CMOS latch.

14. A method for converting a differential logic signal to a single-ended logic signal, comprising:

processing a differential logic signal using current-controlled complementary metal-oxide semiconductor (C³MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to a differential input signal;

converting the processed differential logic signal to a single-ended logic signal using a converter having a regenerative complementary metal-oxide semiconductor (CMOS) latch that is controlled by a self-regulating current pulse responsive to the processed differential logic signal; and

processing the single-ended logic signal using standard CMOS logic.

15. The method of claim 14, wherein converting the differential logic signal to a single-ended logic signal comprises:

receiving the processed differential logic signal at inputs of a differential input circuit;

generating a self-regulating current pulse at one of two outputs of the differential input circuit in response to the processed differential logic signal; and

switching the state of the regenerative CMOS latch in response to the self-regulating current pulse.

16. The method of claim 14, wherein the regenerative CMOS latch switches from rail to rail generating a rail-to-rail single-ended logic signal.