Regenerative signal level converter
First Claim
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1. A complementary metal-oxide-semiconductor (CMOS) circuit for converting a differential logic signal to a single-ended logic signal, comprising:
- a differential input stage coupled to receive the differential logic signal and configured to steer current into a first output branch or a second output branch in response to the differential logic signal;
a first output transistor having a gate terminal coupled to the first output branch;
a second output transistor having a gate terminal coupled to the second output branch; and
a CMOS latch coupled between the first output transistor and the second output transistor.
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Abstract
Method and circuitry for converting a differential logic signal to a single-ended logic signal that minimize delay. In specific embodiments differential logic signals of the type employed in, for example, current-controlled complementary metal-oxide-semiconductor (C3MOS) logic are converted to single-ended rail-to-rail CMOS logic levels using the regenerative action of a
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Citations
16 Claims
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1. A complementary metal-oxide-semiconductor (CMOS) circuit for converting a differential logic signal to a single-ended logic signal, comprising:
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a differential input stage coupled to receive the differential logic signal and configured to steer current into a first output branch or a second output branch in response to the differential logic signal;
a first output transistor having a gate terminal coupled to the first output branch;
a second output transistor having a gate terminal coupled to the second output branch; and
a CMOS latch coupled between the first output transistor and the second output transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
a first node coupled to the first output transistor;
a second node coupled to the second output transistor;
a first inverter having an input coupled to the first node and an output coupled to the second node; and
a second inverter having an input coupled to the second node and an output coupled to the first node.
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3. The CMOS circuit of claim 2 wherein when the differential logic signal signals a first logic state, the differential input stage activates the first output transistor, and when the differential logic signal signals a second logic state, the differential input stage activates the second output transistor.
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4. The CMOS circuit of claim 3 wherein the first output transistor is configured such that when it is activated it applies a self-regulating current pulse to the first node.
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5. The CMOS circuit of claim 4 wherein the second output transistor is configured such that when it is activated it applies a self-regulating current pulse to the second node.
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6. The CMOS circuit of claim 1 wherein the differential input stage comprises:
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first and second differential input transistors coupled to receive the differential logic signal;
first and second load devices respectively coupling the first and second differential input transistors to a power supply node; and
a current source coupled to a common-source terminal of the first and second differential input transistors.
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7. The CMOS circuit of claim 6 wherein the first output transistor comprises the gate terminal coupled to the first differential input transistor, a first current-carrying terminal coupled to the power supply node and a second current carrying terminal coupled to a first node of the CMOS latch.
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8. The CMOS circuit of claim 7 wherein the second output transistor comprises the gate terminal coupled to the second differential input transistor, a first current-carrying terminal coupled to the power supply node and a second current carrying terminal coupled to a second node of the CMOS latch.
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9. The CMOS circuit of claim 8 wherein the first and second differential input transistors comprise n-channel transistors, the first and second load devices comprise p-channel transistors, the current-source comprises an n-channel transistor, and the first and second output transistors comprise p-channel transistors.
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10. The CMOS circuit of claim 6 wherein the first and second load devices comprise transistors.
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11. The CMOS circuit of claim 6 wherein the first and second load devices comprise resistors.
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12. A complementary metal-oxide-semiconductor (CMOS) circuit comprising:
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a first circuit implemented in current-controlled CMOS (C3MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to a differential input signal;
a differential signal to single-ended signal converter coupled to the first circuit, the converter having a CMOS latch that is configured to switch states in response to a self-regulating current pulse that is generated in response to the differential input signal, thereby converting the differential signal from the first circuit to a single-ended CMOS logic signal; and
a second circuit coupled to the converter to receive the single-ended CMOS logic signal and implemented in standard CMOS logic wherein substantially zero static current is dissipated. - View Dependent Claims (13)
a differential pair input structure having a first branch with a first input transistor coupled to a first load device, and a second branch with a second input transistor coupled to a second load device, and a current source coupled to the first and second input transistors;
a first output transistor coupled to the first branch and to a first node of the CMOS latch; and
a second output transistor coupled to the second branch and to a second node of the CMOS latch.
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14. A method for converting a differential logic signal to a single-ended logic signal, comprising:
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processing a differential logic signal using current-controlled complementary metal-oxide semiconductor (C3MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to a differential input signal;
converting the processed differential logic signal to a single-ended logic signal using a converter having a regenerative complementary metal-oxide semiconductor (CMOS) latch that is controlled by a self-regulating current pulse responsive to the processed differential logic signal; and
processing the single-ended logic signal using standard CMOS logic. - View Dependent Claims (15, 16)
receiving the processed differential logic signal at inputs of a differential input circuit;
generating a self-regulating current pulse at one of two outputs of the differential input circuit in response to the processed differential logic signal; and
switching the state of the regenerative CMOS latch in response to the self-regulating current pulse.
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16. The method of claim 14, wherein the regenerative CMOS latch switches from rail to rail generating a rail-to-rail single-ended logic signal.
Specification