Non-volatile memory with temperature-compensated data read

• US 6,560,152 B1
• Filed: 11/02/2001
• Issued: 05/06/2003
• Est. Priority Date: 11/02/2001
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Cernea, Raul-Adrian
• Primary Examiner(s): Lam, David
• Application Number:
  US10/053,171
• Time in Patent Office: 550 Days
• Field of Search: 365/211, 365/189.09, 365/185.22, 365/185.23, 365/185.24, 365/242
• US Class Current: 365/211
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A novel non-volatile memory is disclosed. The non-volatile memory includes an array of data storage cells that individually include a storage element such as a floating gate, a control gate and first and second source/drain terminals. A current source provides a current to the first source/drain terminal of the data storage element. A node is electrically connected to the second source/drain terminal of the data storage element. A bias circuit provides a bias voltage to the node. The bias voltage varies with temperature in a manner approximately inverse to the thermal variation of the threshold voltage of the data storage element. A control gate voltage circuit provides a voltage level to the control gate of the data storage cell.

Claims

1. A non-volatile memory, comprising:

a data storage cell including a storage element, a control gate and first and second source/drain terminals;

a first current source operable to provide a first current to the first source/drain terminal;

a node electrically connected to the second source/drain terminal;

a bias circuit operable to provide a bias voltage to the node, the bias voltage varying with temperature, the variation of the bias voltage being approximately inverse to a thermal variation of a threshold voltage of the data storage cell; and

a control gate voltage circuit operable to provide a voltage level to the control gate.

2. The non-volatile memory of claim 1, further comprising a data sense circuit coupled to the first source/drain terminal of the data storage cell, the data sense circuit being operable to sense a voltage at the first source/drain.

3. The non-volatile memory of claim 1, wherein the bias circuit comprises:

a second current source connected to the node;

a reference voltage generator operable to generate a reference voltage, the reference voltage being invariant with temperature; and

a bias transistor having a first source/drain terminal coupled to the node, the bias transistor having a gate terminal coupled to the reference voltage generator.

4. The non-volatile memory of claim 1, wherein the control gate voltage circuit is operable to provide a predetermined sequence of voltage levels to the control ate of the data storage element during a read cycle of the data storage element.

5. A non-volatile memory comprising:

means for storing data, the means comprising a charge storage element, a control ate and first and second source/drain terminals;

means for providing a first current to the first source/drain terminal of the data storage means;

means for providing a bias voltage to the second source/drain terminal of the data storage means, the bias voltage varying with temperature, the variation of the bias voltage being approximately inverse to a thermal variation of a threshold voltage of the data storage means; and

means for providing a voltage level to the control gate of the data storage element.

6. The non-volatile memory of claim 5, further comprising means for sensing a voltage at the first source/drain terminal of the data storage means.

7. The non-volatile memory of claim 6, wherein the means for providing the bias voltage comprises:

means for drawing a second current from the second source/drain terminal of the data storage means;

means for generating a reference voltage, the reference voltage being approximately invariant with temperature; and

a bias transistor having a first source/drain terminal coupled to the second source/drain terminal of the data storage means, the bias transistor having a gate terminal coupled to the means for generating the reference voltage.

8. The non-volatile memory of claim 7, wherein the means for providing a voltage level to the control gate of the data storing means is operable to provide a predetermined sequence of voltage levels to the control gate of the data storing means during a read cycle of the data storing means.

9. A method for reading stored data from a non-volatile memory, comprising:

conducting a first current through a first source/drain terminal of an EEPROM transistor, the EEPROM transistor having a second source/drain terminal coupled to a node;

conducting current through the node by a current source;

providing a thermally invariant bias voltage to a gate of a transistor, the transistor having a source/drain terminal coupled to the node, the transistor conducting at least a portion of the current being passed through the node by the current source;

providing a voltage to a control gate of the EEPROM transistor; and

detecting a voltage at the first source/drain terminal of the EEPROM transistor.

10. The method of claim 9, further comprising:

providing a sequence of voltages to the control gate of the EEPROM transistor;

detecting a decline in the voltage at the first source/drain terminal of the EEPROM transistor; and

determining, from the decline in the voltage at the first source/drain terminal of the EEPROM transistor, which voltage of the sequence of voltages causes the EEPROM transistor to conduct.

11. The method of claim 10, further comprising determining a numerical value stored by the EEPROM transistor in response to the determination of the voltage that causes the EEPROM transistor to conduct.

12. A method of operating an array of non-volatile memory cells that individually have at least one storage element positioned over at least a portion of a channel between source/drain terminals and a control gate coupled with said at least one storage element, comprising:

addressing one or more of the cells for simultaneously reading or programming data therein,

applying a level of electrical supply to at least one of the source/drain terminals of the addressed cells that varies as a function of a temperature of the memory cell array, and

applying a set of voltages to the control gates of the addressed cells that are independent of the temperature of the memory cell array.