Frequency detector

• US 6,560,305 B1
• Filed: 10/07/1998
• Issued: 05/06/2003
• Est. Priority Date: 10/15/1997
• Status: Expired due to Term

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Croughwell, Rosamaria
• Primary Examiner(s): Liu, Shuwang
• Application Number:
  US09/168,369
• Time in Patent Office: 1,672 Days
• Field of Search: 375/375, 375/376, 375/374, 375/371, 375/373, 375/326, 375/327, 375/360, 327/12, 327/147, 327/148, 327/156, 327/157, 327/236, 331/1.A, 331/1.R, 331/11, 331/12
• US Class Current: 375/376
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00

Abstract

A frequency detection system for producing clock pulses having a frequency equal to the frequency of a stream of binary data. The system includes a voltage controlled oscillator for producing the clock pulses. The frequency of such clock pulses changes in accordance with a control signal. Each one of the clock pulses has four sequential, one-quarter period phases. Adjacent phases are separated by boundaries to divide each clock pulse period into four quadrants. A frequency detector is fed by detected edges of the stream of binary data and the clock pulses for producing the control signal in accordance with the difference in frequency between the frequency of the clock pulses and the frequency of the stream of binary data. A lock-out circuit prevents subsequent production of the control signal until a subsequently detected data edge crosses a different one of the boundaries.

Claims

1. A frequency detection system for producing clock pulses having a frequency equal to the frequency of a stream of binary data, comprising:

(A) a voltage controlled oscillator for producing the clock pulses, the frequency of such clock pulses changing in accordance with a control signal, each one of the clock pulses having four sequential, one-quarter period phases, adjacent phases being separated by boundaries;

(B) a frequency detector fed by detected edges of the stream of binary data and the clock pulses for producing the control signal in accordance with the difference in frequency between the frequency of the clock pulses and the frequency of the stream of binary data, such frequency detector comprising;

(i) a pair of clock pulse/detected data edge latches fed by the clock pulses and the detected edges of the stream of binary data, one of such latches storing a binary signal indicating when a detected edge occurs during one of a first pair of sequential phases of the four phases of the clock pulse and another one of latches producing a binary signal indicating when a detected edge occurs during the other one of the first pair of sequential phases of the four phases of the clock pulse;

(ii) a network, fed by the clock pulse/detected data edge latches, the clock pulses produced by the voltage controlled oscillator, and a block/unblock control signal, adapted to produce the control signal when a detected edge crosses the boundary between first and second quadrants and when the block/unblock control signal is in an unblock condition;

(iii) a lock-out circuit adapted to produce the block/unblock control signal to place the network in a block condition to prevent subsequent production of the control signal and to maintain such block condition until a subsequently detected edge crosses a different one of the boundaries to thereby place the network in the unblock condition.

2. A frequency detection system for producing clock pulse having a frequency equal to the frequency of a stream of binary data, comprising:

(A) a voltage controlled oscillator for producing the clock pulses, the frequency of such clock pulses changing in accordance with a control signal, each one of the clock pulses having four sequential, one-quarter period phases;

(B) a frequency detector fed by detected edges of the stream of binary data and the clock pulses for producing the control signal in accordance with the difference in frequency between the frequency of the clock pulses and the frequency of the stream of binary data, such frequency detector comprising;

(i) a pair of clock pulse/detected data edge latches fed by the clock pulses and the detected edges of the stream of binary data, one of such latches storing a binary signal indicating when a detected edge occurs during one of a first pair of sequential phases of the four phases of the clock pulse and another one of latches producing a binary signal indicating when a detected edge occurs during the other one of the first pair of sequential phases of the four phases of the clock pulse;

(ii) a plurality of boundary crossing detection flip-flops, fed by the clock pulse/detected data edge latches and by the clock pulses produced by the voltage controlled oscillator, adapted to produce the control signal to change the frequency of the clock pulses produced by the voltage controlled oscillator, such control signal being produced when one of the detected edges is in one of the first pair of sequential phases of the four phases of the clock pulse during one of the clock pulses and is in the other one of the first pair of sequential phases of the four phases of the clock pulse during a succeeding one of the clock pulses;

(iii) a lock-out circuit for preventing subsequent production of the control signal until a subsequently detected data edge occurs during a second, different pair of the sequential phases of the clock pulse.

3. A frequency detection system for producing clock pulses having a frequency equal to the frequency of a stream of binary data, comprising:

(A) a voltage controlled oscillator for producing the clock pulses, the frequency of the clock pulses changing in accordance with a control signal, each one of the clock pulses having four sequential, one-quarter period phases;

(B) a frequency detector fed by detected edges of the stream of binary data and the clock pulses for producing the control signal in accordance with the difference in frequency between the clock pulses and the stream of binary data, such frequency detector comprising;

(i) a pair of latches fed by the clock pulses and the detected edges of the stream of binary data, one of such latches storing a binary signal indicating when a detected edge occurs during one of a first pair of sequential phases of the four phases of the clock pulse and another one of latches producing a binary signal indicating when a detected edge occurs during the other one of the first pair of sequential phases of the four phases of the clock pulse;

(ii) a first pair of flip-flops, each one being fed by a corresponding one of the pair of latches and by the clock pulses produced by the voltage controlled oscillator, one of the first pair of flip-flops shifting the binary signal stored in the one of the pair of latches fed thereto in response to one of the edges of each one of the clock pulses, another one of the first pair of flip-flops shifting the binary signal stored in the another one of the pair of latches fed thereto in response to one of the edges of each one of the clock pulses;

(iii) a lock-out circuit for preventing subsequent production of the control signal until a subsequently detected edge occurs during a second, different pair of the sequential phases of the four phases of the clock pulse, such lock-out circuit comprising a pair of gates coupled to outputs of the pair of latches and responsive to a block/unblock control signal, such block/unblock control signal being in an unblock condition when a detected edge occurs during the second, different pair of the sequential phases of the four phases of the clock pulse and for producing a block condition when a pair of successive detected edges occur in the first pair of sequential phases of the clock pulses;

(iv) a second pair of flip-flops fed by the pair of gates, each one of the second pair of flip-flops being fed by a corresponding one of the first pair of flip-flops and by the clock pulses produced by the voltage controlled oscillator, one of the second pair of flip-flops shifting the binary signal stored in one of the first pair of flip-flops fed thereto in response to one of the edges of each one of the clock pulses, during the unblock condition and being inhibited from such shifting by the lock-out circuit during the block condition, another one of the second pair of flip-flops shifts the binary signal stored in another one of the first pair of flip-flops fed thereto in response to one of the edges of each one of the clock pulses during the unblock condition and being inhibited from such shifting by the lock-out circuit during the block condition;

and wherein the outputs of the second pair of flip-flops are used to generate the control signal to the voltage controlled oscillator.

4. A frequency detection system for producing clock pulses having a frequency equal to the frequency of a stream of binary data, comprising:

(A) a voltage controlled oscillator, for producing an in-phase clock pulse, CKI, and a quadrature clock pulse, CKQ, shifted in time from the in-phase clock pulse one quarter of a clock pulse period, each clock pulse period being separated into four sequential phases, a first phase occurring when the in-phase clock pulse is at a first state and the quadrature clock pulse is in a second state, a second phase occurring when the in-phase clock pulse is in the first state and the quadrature clock pulse is in the first state, a third phase occurring when the in-phase clock pulse is in the second state and the quadrature clock pulse is in the first state, and a fourth phase occurring when the in-phase clock pulse is in the second state and the quadrature clock pulse is in the second state, the first, second, third and fourth phases being separated by first, second, third and fourth boundaries, respectively, the clock pulses, CKI and CKQ, having a frequency which changes in accordance with a control signal;

(B) a frequency detector fed by detected edges of the stream of binary data and the clock pulses for producing the control signal in accordance with the difference in frequency between the frequency of the clock pulses and the frequency of the stream of binary data such frequency detector comprising;

(i) a first pair of logic gates fed by the in-phase and quadrature clock pulses, one of such gates producing a logic signal having a logic state indicating when a detected edge occurs during one of a first pair of sequential phases of the four phases of the clock pulses and another one of the first pair of logic gates producing a logic signal having the logic state indicating when a detected edge occurs during the other one of the first pair of sequential phases of the four phasesof the clock pulses the first pair of sequential phases of the four phases of the clock pulses occurring when one of the in-phase and quadrature clock pulses is in the first state and the other one of the in-phase and quadrature clock pulses is in the second state during one portion of the clock pulse period and changes the logic state during a succeeding portion of the clock pulse period;

(ii) a pair of latches, each one thereof being fed by a corresponding one of the first pair of gates and the detected edges of the stream of binary data, one of such latches storing a binary signal indicating when a detected edge occurs during one of the first pair of sequential phases of the four phases of a the clock pulses and another one of latches producing a binary signal indicating when a detected edge occurs during the other one of the first pair of sequential phases of the four phases of the clock pulses;

(iii) a first pair of flip-flops, each one being fed by a corresponding one of the pair of latches and by the clock pulses produced by the voltage controlled oscillator, one of the first pair of flip-flops shifting the binary signal stored in the one of the pair of latches fed thereto in response to one of the edges of each one of the clock pulses, another one of the first pair of flip-flops shifting the binary signal stored in the another one of the pair of latches fed thereto in response to one of the edges of each one of the clock pulses;

(iv) a lock-out circuit for preventing subsequent production of the control signal until a subsequently detected edge occurs during a second, different pair of the sequential phases of the four phases of the clock pulses, such lock-out circuit comprising a second pair of logic gates coupled to outputs of the pair of latches and responsive to a block/unblock control signal, such block/unblock control signal being in an unblock condition when a detected edge occurs during the second, different pair of the sequential phases of the four phases of the clock pulses and for producing a block condition when a pair of successive detected edges occur in the first pair of sequential phases of the four phases of the clock pulses;

(v) a second pair of flip-flops fed by the second pair of logic gates, each one of the second pair of flip-flops being fed by a corresponding one of the first pair of flip-flops and by the clock pulses produced by the voltage controlled oscillator, one of the second pair of flip-flops shifting the binary signal stored in one of the first pair of flip-flops fed thereto in response to one of the edges of each one of the clock pulses during the unblock condition and being inhibited from such shifting by the lock-out circuit during the block condition, another one of the second pair of flip-flops shifting the binary signal stored in another one of the first pair of flip-flops fed thereto in response to one of the edges of each one of the clock pulses during the unblock condition and being inhibited from such shifting by the lock-out circuit during the block condition;

and wherein the outputs of the second pair of flip-flops are used to generate signal.

5. A frequency detection system for producing clock pulses having a frequency equal to the frequency of a stream of binary data, comprising:

(A) a charge pump;

(B) a voltage controlled oscillator, for producing an in-phase clock pulse, CKI, and a quadrature clock pulse, CKQ, shifted in time from the in-phase clock pulse one quarter of a clock pulse period, each clock pulse period being separated into four sequential phases a first phase occurring when the in-phase clock pulse is at a first state and the quadrature clock pulse is in a second state, a second phase occurring when the in-phase clock pulse is in the first state and the quadrature clock pulse is in the first state, a third phase occurring when the in-phase clock pulse is in the second state and the quadrature clock pulse is in the first state, and a fourth phase occurring when the in-phase clock pulse is in the second state and the quadrature clock pulse is in the second state, the first, second, third and fourth phases being separated by first, second, third and fourth boundaries, respectively, the clock pulses, CKI and CKQ, having a frequency which changes in accordance with an output signal produced by the charge pump;

(C) a frequency detector fed detected edges of the stream of binary data and the in-phase and quadrature clock pulses, such frequency detector comprising;

(i) a first pair of logic gates fed by the in-phase and quadrature clock pulses, one of such gates producing a logic signal having a logic state indicating, when a detected edge occurs during one of a first pair of sequential phases of the phases of the clock pulses and another one of the first pair of logic gates producing a logic signal having the logic state indicating when a detected edge occurs during the other one of the first pair of sequential phases of the four phases of the clock pulses the first pair of sequential phases of the four phases of the clock pulses occurring when one of the in-phase and quadrature clock pulses is in the first state and the other one of the in-phase and quadrature clock pulses is in the second state during one portion of the clock pulse period and changes the logic state during a succeeding portion of the clock pulse period;

(ii) a pair of latches each one thereof being fed by a corresponding one of the first pair of logic gates and the detected edges of the stream of binary data, one of such latches storing a binary signal indicating when a detected edge occurs during one of the first pair of sequential phases of the four phases of the clock pulses and another one of the latches producing a binary signal indicating when a detected edge occurs during the other one of the first pair of sequential phases of the four phases of the clock pulses;

(iii) a first pair of flip-flops, each one being fed by a corresponding one of the pair of latches and by the clock pulses produced by the voltage controlled oscillator, one of the first pair of flip-flops shifting the binary signal stored in the one of the pair of latches fed thereto in response to one of the edges of each one of the clock pulses, another one of the first pair of flip-flops shifting the binary signal stored in the another one of the pair of latches fed thereto in response to one of the edges of each one of the clock pulses;

(iv) a lock-out circuit for preventing subsequent production of the control signal until a subsequently detected edge occurs during a second, different pair of the sequential phase of the four phases of the clock pulses, such lock-out circuit comprising a second pair of logic gates coupled to outputs of the first pair of flip-flops and responsive to a block/unblock control signal, such block/unblock control signal being in an unblock condition when a detected edge occur during a second, different pair of the sequential phases of the four phases of the clock pulses and for producing a block condition when a pair of successive detected edges occur in the first pair of sequential phases of the four phases of the clock pulses;

(v) a second pair of flip-flops fed by the second pair of logic gates, each one of the second pair of flip-flops being fed by a corresponding one of the first pair of flip-flops and by the clock pulses produced by the voltage controlled oscillator, one of the second pair of flip-flops shifting the binary signal stored in one of the first pair of flip-flops fed thereto in response to one of the edges of each one of the clock pulses during the unblock condition and being inhibited from such shifting by the lock-out circuit during the block condition, another one of the second pair of flip-flops shifting the binary signal stored in another one of the first pair of flip-flops fed thereto in response to one of the edges of each one of the clock pulses during the unblock condition and being inhibited from such shifting by the lock-but circuit during the block condition;

and wherein the outputs of the second pair of flip-flops are fed to the charge pump as pump-up and pump-down signals.