Phase locked loop (PLL) with linear parallel sampling phase detector

• US 6,560,306 B1
• Filed: 12/17/1999
• Issued: 05/06/2003
• Est. Priority Date: 06/19/1997
• Status: Expired due to Term

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Navabi, Mohammad J., Duffy, Michael L.
• Primary Examiner(s): Liu, Shuwang
• Application Number:
  US09/465,565
• Time in Patent Office: 1,236 Days
• Field of Search: 375/376, 375/354, 375/374, 375/375, 375/326, 375/327, 375/373, 331/1.A, 331/11, 327/242, 327/12, 327/147, 327/148, 327/156, 327/157, 327/236, 381/15
• US Class Current: 375/376
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence

Abstract

A parallel sampling phase detector with linear output response. The parallel sampling phase detector for use in data recovery. The device includes a voltage controlled oscillator (VCO) that generates ten separate phase signals using a five stage ring oscillator. Five linear phase detectors are employed in the device, each operating during one of five “window” intervals. The “window” intervals are non-overlapping, and are generated using preselected ones of the VCO output phases. The linear phase detectors each generate, respectively, a variable pulsewidth pump up signal wherein the pulsewidth of the pump up signal is proportional to a phase difference between the input data signal applied to the phase detector, and the output phase signals of the VCO. Each phase detector also generates a pump down signal that has a fixed pulsewidth. A loop filter determines the difference between the pump up and pump down signals and develops a control signal to vary the output frequency and phase of the VCO in accordance therewith. Each phase detector also operates as a deserializer, capturing, during the interval when the respective “window” signal is active, the data signal from the input data stream. The plurality of sampled data signals are captured by a data register, which then outputs an n-bit (5-bit) parallel format data word. The linear phase detector includes means for generating the pump down signal in response to the generation of the pump up signal.

Claims

1. An apparatus configured to receive an input data signal having a phase and generate an output signal having a plurality of phases comprising:

a plurality of phase detector circuits each configured to receive said input data signal and to generate a respective phase difference signal, each of said respective phase difference signals corresponding to a phase difference between the phase of said input data signal and a respective phase of said output signal, wherein at least one of said phase detectors includes (i) a first memory element configured to generate a sampled data signal in response to said input data signal, (ii) a function gate configured to generate a first pump signal in response to said input data signal and said sampled data signal, and (iii) a second circuit configured to generate a second pump signal in response to said first pump signal; and

a circuit configured to generate the respective phases of said output signal in response to said phase difference signals.

2. The apparatus of claim 1, wherein each of said respective phase difference signals is proportional to the phase difference between the phase of said input data signal and the respective phase of said output signal.

3. The apparatus of claim 1, wherein each of said phase detector circuits includes a logic circuit configured to generate a window signal in response to a plurality of clock signals.

4. The apparatus of claim 1, wherein each phase detector circuit includes a respective logic circuit for generating a plurality of window signals, said window signals each having a respective active state and a respective inactive state wherein said window signals are non-overlapping in said active state.

5. The apparatus of claim 1, wherein at least one of said phase difference signals has a variable pulsewidth.

6. The apparatus of claim 3, wherein said first memory element is configured to generate said sampled data signal when said window signal is active.

7. The apparatus of claim 1, wherein each phase detector circuit is configured to generate a respective sampled data signal, said apparatus further including a register for storing an n-bit data word in response to said sampled data signals.

8. The apparatus of claim 1 wherein said circuit includes a loop filter configured to generate a control signal varying in magnitude as a function of said phase difference signals.

9. The apparatus of claim 1 wherein said circuit includes a voltage-controlled oscillator (VCO) configured to generate said plurality of phases of said output signal.

10. The apparatus of claim 9 wherein said VCO comprises a ring oscillator having a plurality of stages.

17. The apparatus according to claim 3, wherein said function gate comprises an enable terminal for receiving said window signal.

20. The apparatus according to claim 1, wherein (i) said second circuit comprises a second memory circuit, (ii) said first pump signal comprises a pump up signal and said second pump signal comprises a pump down signal, and (iii) said phase difference signal comprises said first and second pump signals.

22. The apparatus according to claim 7, wherein n equals the number of said plurality of phase detector circuits.

11. A parallel sampling phase detector apparatus comprising;

a plurality of phase detector circuits each configured to receive an input data signal, said phase detector circuits being configured to generate a phase difference signal, each of said phase difference signals corresponding to a phase difference between the phase of said input data signal and a respective phase of an output signal, wherein at least one of said phase detectors includes (i) a first memory element configured to generate a sampled data signal in response to said input data signal, (ii) a function gate configured to generate a pump signal in response to said input data signal and said sampled data signal, and (iii) a second circuit configured to generate a second pump signal in response to said first pump signal;

a loop filter configured to generate a control signal in response to said phase difference signals; and

a voltage controlled oscillator (VCO) configured to generate said output signal in response to said control signal wherein said output signal has a plurality of phases, wherein each phase detector circuit operates according to at least one preselected phase of said VCO output signal.

12. The phase detector apparatus of claim 11 wherein at least one of said phase detector circuits includes a logic circuit configured to generate a window signal in response to preselected ones of said plurality of phases of said VCO output signal.

13. The phase detector apparatus of claim 11, wherein each phase detector circuit includes a respective logic circuit for generating a plurality of window signals, said window signals each having a respective active state and a respective inactive state wherein said window signals are non-overlapping in said active state.

18. The apparatus according to claim 12, wherein said function gate comprises an enable terminal for receiving said window signal.

14. A method of recovering data from an input data signal comprising the steps of:

(A) generating, for each one of a plurality of linear output phase detectors, (a) a respective phase difference signal in response to said input data signal, wherein each phase difference signal corresponds to a respective phase difference between the phase of said input data signal and a respective phase of an output signal and at least one of said phase detectors includes (i) a first memory element configured to generate a sampled data signal in response to said input data signal and (ii) a function gate configured to generate a first pump signal in response to said input data signal and said sampled data signal and (b) a second pump signal;

(B) generating the respective phases of said output signal in response to the phase difference signals; and

(C) determining and storing a plurality of bit values during respective bit periods of said input data signal in response to said phases of said output signal.

15. The method of claim 14 further including the step of;

storing said bit values to thereby form a parallel-bit data word.

16. The method of claim 14 wherein step (C) includes the substeps of:

generating a window signal for each linear phase detector in response to preselected phases of said output signal, only one of said window signals being active at a time; and

generating, for each linear phase detector, the sampled data signal when a respective one of said window signals becomes active.

19. The method according to claim 16, wherein said function gate comprises an enable terminal for receiving said window signal.

21. The method according to claim 14, wherein (i) said first pump signal comprises a pump up signal and said second pump signal comprises a pump down signal, (ii) at least one of said first and second pump signals have a pulsewidth that varies according to a respective one of said phase differences, and (iii) said phase difference signals comprise said first and second pump signals.