MOS transistors substitute circuit having a transformer/data interface function, particularly for ISDN networks and corresponding control and driving switch configuration

• US 6,560,333 B1
• Filed: 09/23/1998
• Issued: 05/06/2003
• Est. Priority Date: 09/23/1997
• Status: Expired due to Term

• Current Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Lari, Ferdinando, Antonini, Carlo, Consiglio, Pietro
• Primary Examiner(s): Isen, Forester W.
• Assistant Examiner(s): Swerdlow, Daniel
• Application Number:
  US09/159,526
• Time in Patent Office: 1,686 Days
• Field of Search: 307/64, 379/413, 379/405, 370/200
• US Class Current: 379/413
• CPC Class Codes: H04L 12/00 Data switching networks interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units G06F13/00
• CPC Class Codes: H04M 19/08 with current supply sources at the substations generating ringing current H04M19/04
• CPC Class Codes: H04Q 11/0435 Details
• CPC Class Codes: H04Q 2213/13003 Constructional details of switching devices
• CPC Class Codes: H04Q 2213/1308 Power supply
• CPC Class Codes: H04Q 2213/13082 Power supply via phantom line
• CPC Class Codes: H04Q 2213/1309 Apparatus individually associated with a subscriber line, line circuits
• CPC Class Codes: H04Q 2213/13166 Fault prevention
• CPC Class Codes: H04Q 2213/13202 Network termination [NT]
• CPC Class Codes: H04Q 2213/13209 ISDN
• CPC Class Codes: H04Q 2213/13305 Transistors, semiconductors in general
• CPC Class Codes: H04Q 2213/1332 Logic circuits
• CPC Class Codes: H04Q 2213/13322 Integrated circuits
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

The invention relates to a MOS transistors substitutive circuit having a transformer/data interface function, in particular for ISDN networks, comprising first (11a) and second (11b) power supply/transmitter blocks, the first power supply/transmitter block (11a) being connected between a voltage reference (V) and a first data interface (RX), and the second power supply/transmitter block (11b) being connected between a ground potential reference (GND) and a second data interface (TX), both power supply/transmitter blocks being connected to a supply voltage reference (VDD). The MOS transistors substitutive circuit according to the invention comprises first (12) and second (12′) MOS transistor pairs connected to the voltage reference (V), the MOS transistors being diode configured and held in their saturation range, so as to have a high A.C. impedance and virtually zero D.C. impedance, thereby minimizing power dissipation through the substitutive circuit.

The invention also concerns a control and driving switch configuration for a network termination of at least first (11) and second (11′) MOS transistors substitutive circuits according to the invention, operating respectively in a first condition (“normal condition”) of operation of the network termination characterized by the presence of the polarity reverse control signal (Scrp), and a second condition (“RM emergency condition”) of operation of the network termination characterized by the absence of the polarity reverse control signal (Scrp). The control configuration selects the voltage reference being applied to the power supply/transmitter blocks.

Claims

1. A MOS transistors substitutive circuit having a transformer/data interface function for ISDN networks, said substitutive circuit comprising:

a voltage reference terminal;

a supply voltage reference terminal;

a ground potential reference terminal;

a first data interface;

a second data interface;

a first power supply/transmitter block, the first power supply/transmitter block being connected between the voltage reference terminal and the first data interface, and being further connected to the supply voltage reference terminal, the first power supply/transmitter block including;

a first MOS transistor coupled between the voltage reference terminal and the first data interface, and being diode configured; and

a second MOS transistor coupled between the voltage reference terminal and the first data interface, and being diode configured; and

a second power supply/transmitter block, the second power supply/transmitter block being connected between the ground potential reference terminal and the second data interface, and being further connected to the supply voltage reference terminal, the second power supply/transmitter block including;

a third MOS transistor coupled between the ground potential reference terminal and the second data interface, and being diode configured; and

a fourth MOS transistor coupled between the ground potential reference terminal and the second data interface, and being diode configured,

wherein the first and second power supply/transmitter blocks emulate transformers for an ISDN telephone line by performing the data interface function of transmitting data presented on the line and the transformer function of transmitting a power supply to a terminal apparatus, while satisfying the ISDN network interface circuit requirements for low power dissipation.

2. The MOS transistors substitutive circuit of claim 1, wherein the first, second, third, and fourth MOS transistors are all held in their saturation range, so as to have a high A.C. impedance and virtually zero D.C. impedance that minimizes power dissipation through the substitutive circuit.

3. The MOS transistors substitutive circuit of claim 1, wherein:

the circuit can be operated in a first condition of operation in which the voltage reference terminal is connected to a remote supply voltage characterized by a first current polarity and the presence of a polarity reverse control signal; and

the circuit can be operated in a second condition of operation in which the voltage reference terminal is connected to an emergency voltage characterized by a second current polarity that is reversed from the first current polarity and the absence of the polarity reverse control signal.

4. The MOS transistors substitutive circuit of claim 1, wherein the first and second MOS transistors are of a first conductivity type, and the third and fourth MOS transistors are of a second conductivity type.

5. The MOS transistors substitutive circuit of claim 4, wherein the first, second, third, and fourth MOS transistors are realized in integrated circuit form using a conventional mixed technology of the BCD type.

7. A control and driving switch configuration for substitutive transformer/data transmitter circuits in a network termination for an ISDN network, the network termination comprising a first converter connected to a ground potential reference terminal, delivering a supply voltage and an emergency voltage, and a second converter connected to the ground potential reference terminal, delivering a remote supply voltage, the configuration comprising:

at least a first and a second MOS transistors substitutive circuit according to claim 1, which circuits respectively operate in a first condition of operation of the network termination characterized by a first current polarity and the presence of a polarity reverse control signal, and a second condition of operation of the network termination characterized by a second current polarity that is reversed from the first current polarity and the absence of the polarity reverse control signal.

8. The control configuration of claim 7, further comprising:

a first data interface;

a second data interface; and

a signal line, wherein the first MOS transistors substitutive circuit is connected to the signal line whereon is present the polarity reverse control signal which is generated by the second converter of the network termination, and is connected to the first data interface, and wherein the second MOS transistors substitutive circuit is connected to the signal line, and is connected to the second data interface.

9. The control configuration of claim 8, wherein:

the configuration further comprises a first logic inverter and a second logic inverter; and

the first MOS transistors substitutive circuit further comprises;

a first normal supply block, receiving the remote supply voltage from the second converter, and being connected to the signal line through the first logic inverter and to the first data interface; and

a second normal supply block being connected to the signal line through the second logic inverter, and connected to the second data interface.

10. The control configuration of claim 9, wherein:

the configuration further comprises a current limiter; and

the second MOS transistors substitutive circuit comprises;

a first emergency supply block, receiving the emergency voltage from the first converter through the current limiter, and being connected to the second normal supply block and to the second data interface; and

a second emergency supply block, connected to the first normal supply block and to the first data interface.

11. The control configuration of claim 10, wherein in the first condition of operation of the network termination, the remote supply voltage is present, which voltage passes through the first normal supply block to the first data interface, and from the second data interface to the ground potential reference terminal through the second normal supply block.

12. The control configuration of claim 11, wherein in the second condition of operation of the network termination, the emergency voltage is present, and the polarity reverse control signal present on the signal line enables the emergency supply blocks and disables the normal supply blocks through the first and second logic inverters.

6. A MOS transistors substitutive circuit having a transformer/data interface function for ISDN networks, said substitutive circuit comprising:

a voltage reference terminal;

a supply voltage reference terminal;

a ground potential reference terminal;

a first data interface;

a second data interface;

a first power supply/transmitter block, the first power supply/transmitter block being connected between the voltage reference terminal and the first data interface, and being further connected to the supply voltage reference terminal;

a second power supply/transmitter block, the second power supply/transmitter block being connected between the ground potential reference terminal and the second data interface, and being further connected to the supply voltage reference terminal;

a first MOS transistor coupled between the voltage reference terminal and the first data interface, and being diode configured;

a second MOS transistor coupled between the voltage reference terminal and the first data interface, and being diode configured;

a third MOS transistor coupled between the ground potential reference terminal and the second data interface, and being diode configured;

a fourth MOS transistor coupled between the ground potential reference terminal and the second data interface, and being diode configured;

a first connection resistor, connected between the gate of the first MOS transistor and the lead of the first MOS transistor which is coupled to the first data interface such that the first MOS transistor is diode configured through the first connection resistor;

a second connection resistor, connected between the gate of the second MOS transistor and the lead of the second MOS transistor which is coupled to the first data interface such that the second MOS transistor is diode configured through the second connection resistor;

a third connection resistor, connected between the gate of the third MOS transistor and the lead of the third MOS transistor which is coupled to the second data interface such that the third MOS transistor is diode configured through the third connection resistor; and

a fourth connection resistor, connected between the gate of the fourth MOS transistor and the lead of the fourth MOS transistor which is coupled to the second data interface such that the fourth MOS transistor is diode configured through the fourth connection resistor.

13. The MOS transistors substitutive circuit of claim 6, wherein:

the gates of the third and fourth MOS transistors are connected together;

the lead of the third MOS transistor which is coupled to the second data interface is the drain;

the lead of the fourth MOS transistor which is coupled to the second data interface is the drain;

the sources of the third and fourth MOS transistors are both coupled to the ground potential reference terminal; and

the second power supply/transmitter block comprises the third and fourth MOS transistors.

14. The MOS transistors substitutive circuit of claim 13, further comprising a sensing resistor disposed between the ground potential reference terminal and the source terminals of the third and fourth MOS transistors.

15. The MOS transistors substitutive circuit of claim 13, wherein the second power supply/transmitter block further comprises:

a first current mirror, connected to the supply voltage reference terminal;

a second current mirror, connected to the supply voltage reference terminal;

a third current mirror, connected to the ground potential reference terminal and to the second current mirror; and

a fourth current mirror, connected to the ground potential reference terminal and to the first current mirror.

16. The MOS transistors substitutive circuit of claim 15, wherein the second power supply/transmitter block further comprises:

a first decoupling element, coupled to the first current mirror, the fourth current mirror, and the drain of the third MOS transistor, such that the first decoupling element is disposed between the drain of the third MOS transistor and both the first and fourth current mirrors;

a second decoupling element, coupled to the second current mirror, the third current mirror, and the drain of the fourth MOS transistor, such that the second decoupling element is disposed between the drain of the fourth MOS transistor and both the second and third current mirrors;

a first decoupling capacitor, coupled to the first current mirror, the fourth current mirror, and the second data interface, such that the first decoupling capacitor is disposed between the second data interface and both the first and fourth current mirrors;

a second decoupling capacitor, coupled to the second current mirror, the third current mirror, and the second data interface, such that the second decoupling capacitor is disposed between the second data interface and both the second and third current mirrors; and

wherein the first and second decoupling elements are utilized under particular conditions of power supply to the MOS transistors substitute circuit.

17. The MOS transistors substitutive circuit of claim 15, wherein the second power supply/transmitter block further comprises:

a first decoupling resistor;

a second decoupling resistor; and

a buffer, the buffer being connected to the first and third current mirrors through the first decoupling resistor, and being connected to the second and fourth current mirrors through the second decoupling resistor.

18. The MOS transistors substitutive circuit of claim 17, further comprising a reference voltage reference terminal, and wherein the buffer is connected between the supply voltage reference terminal and the ground potential reference terminal, and is further connected to the reference voltage reference terminal, thereby setting an output reference voltage for all of the current mirrors, while the decoupling resistors are setting a suitable impedance for an A.C. signal presented to the second data interface.

19. The MOS transistors substitutive circuit of claim 15, wherein the second power supply/transmitter block further comprises a first voltage/current converter comprising a first input terminal which is connected to the first current mirror, and a second input terminal which is connected to the second current mirror.

20. The MOS transistors substitutive circuit of claim 6, wherein:

the gates of the first and second MOS transistors are connected together;

the lead of the first MOS transistor which is coupled to the first data interface is the drain;

the lead of the second MOS transistor which is coupled to the first data interface is the drain;

the sources of the first and second MOS transistors are both coupled to the voltage reference terminal; and

the first power supply/transmitter block comprises the first and second MOS transistors.

21. The MOS transistors substitutive circuit of claim 20, further comprising a reference voltage reference terminal, and wherein the first power supply/transmitter block further comprises:

a second voltage/current converter comprising;

a first input;

a second input;

a first output;

second output;

first terminal connected to the supply voltage reference terminal; and

a second terminal connected to the ground potential reference terminal;

a third decoupling capacitor, disposed between the first input of the second voltage/current converter and the drain of the first MOS transistor;

a fourth decoupling capacitor, disposed between the second input of the second voltage/current converter and the drain of the second MOS transistor;

a first bias resistor, disposed between the first input of the second voltage/current converter and the reference voltage reference terminal; and

a second bias resistor, disposed between the second input of the second voltage/current converter and the reference voltage reference terminal.

22. The MOS transistors substitutive circuit of claim 21, wherein the first power supply/transmitter block further comprises:

a fifth current mirror, connected to the first output of the second voltage/current converter and further connected to the supply voltage reference terminal; and

a sixth current mirror, connected to the second output of the second voltage/current converter and further connected to the supply voltage reference terminal.

23. The MOS transistors substitutive circuit of claim 22, wherein the first power supply/transmitter block further comprises:

a control terminal;

a first amplifier circuit, connected to the fifth current mirror, the supply voltage reference terminal, the ground potential reference terminal, and the control terminal of the first power supply/transmitter block; and

a second amplifier circuit, connected to the sixth current mirror, the supply voltage reference terminal, the ground potential reference terminal, and the control terminal of the first power supply/transmitter block.

24. The MOS transistors substitutive circuit of claim 23, wherein:

the first amplifier circuit comprises a resistor and an output terminal, and wherein there is present on the output terminal an A.C. signal output voltage which is proportional to the line voltage at the first data interface, the voltage being suitably modulatable by means of the fifth and sixth current mirrors and the resistor; and

the second amplifier circuit comprises a resistor and an output terminal, and wherein there is present on the output terminal an A.C. signal output voltage which is proportional to the line voltage at the first data interface, the voltage being suitably modulatable by means of the fifth and sixth current mirrors and the resistor.

25. The MOS transistors substitutive circuit of claim 6, wherein:

the gates of the first and second MOS transistors are coupled together;

the gates of the third and fourth MOS transistors are coupled together;

the values of the first connection resistor and the second connection resistor are the same, thereby canceling, at the common gate terminal of the first MOS transistor and the second MOS transistor any differential signal at the first data interface, and the first MOS transistor and the second MOS transistor offering, therefore, a high impedance to differential signals; and

the values of the third connection resistor and the fourth connection resistor are the same, thereby canceling, at the common gate terminal of the third MOS transistor and the fourth MOS transistor any differential signal at the second data interface, and the third MOS transistor and the fourth MOS transistor offering, therefore, a high impedance to differential signals.

26. The MOS transistors substitutive circuit of claim 6, further comprising a compensation current generator connected across the first, second, third, and fourth connection resistors for extracting and injecting a compensation current homogeneous with the variation of the connection resistors and, accordingly, obtaining a constant voltage drop across the connection resistors effective to further reduce the power dissipated through the substitutive circuit.

27. The MOS transistors substitutive circuit of claim 26, further comprising:

a first match resistor, connected to the gate terminals of the first and second MOS transistors;

a first compensation transistor, wherein the source terminal is connected to the first and second connection resistors, and the gate terminal is connected to the drain terminal, to the compensation current generator, and to the first match resistor, whereby the first compensation transistor is thus diode configured and has a voltage drop which virtually equals a MOS transistor threshold voltage, so as to compensate the threshold voltages of the transistors employed, with respect to temperature and process variations;

a second match resistor, connected to the gate terminals of the third and fourth MOS transistors; and

a second compensation transistor, wherein the source terminal is connected to the third and fourth connection resistors, and the gate terminal is connected to the drain terminal, to the compensation current generator, and to the second match resistor, whereby the second compensation transistor is thus diode configured and has a voltage drop which virtually equals a MOS transistor threshold voltage, so as to compensate the threshold voltages of the transistors employed, with respect to temperature and process variations.

28. The MOS transistors substitutive circuit of claim 27, further comprising:

a reference voltage reference terminal;

a first match current generator, disposed between the reference voltage reference terminal and the first match resistor, such that the first compensation transistor has its source terminal connected to the reference voltage reference terminal through a series of the first match resistor and the first match current generator;

a second match current generator, disposed between the ground potential reference terminal and the second match resistor, such that the second compensation transistor has its source terminal connected to the ground potential reference terminal through a series of the second match resistor and the second match current generator; and

wherein the first and second match current generators thus allow the voltages across the first, second, third, and fourth connection resistors to be modulated through the respective match resistors for optimum adjustment, at the manufacturing stage, of the substitutive circuit, a further reduction of the dissipated power, and inherent compensation of the effects of temperature and process variations on the threshold voltage of the transistors employed.

29. The MOS transistors substitutive circuit of claim 27 wherein:

the first and second MOS transistors comprise MOS transistors of a first type;

the third and fourth MOS transistors comprise MOS transistors of a second type; and

the first compensation transistor is of the same type as the first and second MOS transistors, and the second compensation transistor is of the same type as the third and fourth MOS transistors.

30. A MOS transistors substitutive circuit having a transformer/data interface function, said substitutive circuit comprising:

a first data interface;

a second data interface;

a first power supply/transmitter block, the first power supply/transmitter block being connected between a voltage reference terminal and the first data interface, the first power supply/transmitter block including a first pair of diode configured MOS transistors coupled in parallel between the voltage reference terminal and the first data interface; and

a second power supply/transmitter block, the second power supply/transmitter block being connected between a ground potential reference terminal and the second data interface, the second power supply/transmitter block including a second pair of diode configured MOS transistors coupled in parallel between the ground potential reference terminal and the second data interface.

31. The MOS transistors substitutive circuit of claim 30, wherein the source terminals of the two MOS transistors of the first pair of diode configured MOS transistors are connected in common.

32. The MOS transistors substitutive circuit of claim 31, wherein the source terminals of the two MOS transistors of the second pair of diode configured MOS transistors are connected in common.

33. The MOS transistors substitutive circuit of claim 30,

wherein the gate terminals of the two MOS transistors of the first pair of diode configured MOS transistors are connected in common, and

the gate terminals of the two MOS transistors of the second pair of diode configured MOS transistors are connected in common.

34. The MOS transistors substitutive circuit of claim 30, further comprising:

first and second transistors,

wherein one MOS transistor of the first pair of diode configured MOS transistors has its gate terminal coupled to one terminal of the first resistor and its drain terminal coupled to the other terminal of the first resistor, and

the other MOS transistor of the first pair of diode configured MOS transistors has its gate terminal coupled to one terminal of the second resistor and its drain terminal coupled to the other terminal of the second resistor.