Square wave analog multiplier

• US 6,560,451 B1
• Filed: 10/15/1999
• Issued: 05/06/2003
• Est. Priority Date: 10/15/1999
• Status: Expired due to Term

• Current Assignee: Crystal Semiconductor Corporation (Cirrus Logic Incorporated)
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Somayajula, Shyam S.
• Primary Examiner(s): Chin, Vivian
• Assistant Examiner(s): Lee, John J
• Application Number:
  US09/419,311
• Time in Patent Office: 1,299 Days
• Field of Search: 455/323, 455/318, 455/319, 455/330, 455/333, 455/326, 455/325, 455/313, 455/315, 327/113, 327/355, 327/356, 327/357, 327/358, 327/359, 327/360, 327/361
• US Class Current: 455/318
• CPC Class Codes: H03D 2200/0043 Bias and operating point
• CPC Class Codes: H03D 2200/0047 Offset of DC voltage or frequency
• CPC Class Codes: H03D 7/1433 using bipolar transistors H03D7/145 takes precedence
• CPC Class Codes: H03D 7/1441 using field-effect transistors H03D7/145 takes precedence
• CPC Class Codes: H03D 7/1491 Arrangements to linearise a transconductance stage of a mixer arrangement

Abstract

An analog multiplier or mixer that mixes a signal f_c with a square wave local oscillator improves heterodyning operation of a circuit. In various square wave analog multiplier or mixer embodiments, heterodyning performance is improved in noise reduction, saturation performance, linearity, and other measures by adding a DC current path in parallel to a signal current path of the multiplier or mixer. The parasitic capacitances, noise, and nonlinearity problems in a heterodyning circuit are solved by adding a path to a square wave mixer for carrying the signal current and the DC current on different paths. An apparatus includes a circuit coupled between a first voltage reference and a second voltage reference. The circuit includes a first square wave oscillator branch and a second square wave oscillator branch. The first square wave oscillator branch is driven by a square wave oscillator signal and the second square wave oscillator branch is driven by an inverse of the square wave oscillator signal. The first and second square wave oscillator branches each include a DC current path and a signal current path. The signal current path is driven by the square wave oscillator signal and the inverse of the square wave oscillator signal, respectively.

Claims

1. An apparatus comprising:

a circuit coupled between a first voltage reference and a second voltage reference, the circuit including a first square wave oscillator branch and a second square wave oscillator branch, the first square wave oscillator branch being driven by a square wave oscillator signal and the second square wave oscillator branch being driven by an inverse of the square wave oscillator; and

the first and second square wave oscillator branches each including a DC current path and a signal current path, the signal current path being driven by the square wave oscillator signal and the inverse of the square wave oscillator signal, respectively.

2. The apparatus according to claim 1 further comprising:

a node coupling the first and second square wave oscillator branches; and

a common pathway coupled between the node and the second voltage reference.

3. The apparatus according to claim 1 further comprising:

a node coupling the first and second square wave oscillator branches;

a common pathway coupled between the node and the second voltage reference; and

a system input transistor having a conductive pathway on the common pathway and having a control terminal for control by a system input signal.

4. The apparatus according to claim 1 further comprising:

a node coupling the first and second square wave oscillator branches;

a common pathway coupled between the node and the second voltage reference;

a system input transistor having a conductive pathway on the common pathway and having a control terminal for control by a system input signal; and

a biasing signal coupled to the control terminal of the system input transistor.

5. The apparatus according to claim 1 further comprising:

a node coupling the first and second square wave oscillator branches;

a common pathway coupled between the node and the second voltage reference;

a system input transistor having a conductive pathway on the common pathway and having a control terminal for control by a system input signal;

a biasing signal coupled to the control terminal of the system input transistor;

a biasing resistor on a line coupling the biasing signal to the control terminal of the system input transistor; and

a system input capacitor coupling the system input signal to the control terminal of the system input transistor.

6. The apparatus according to claim 1 wherein:

the DC current paths in the first and second square wave oscillator branches include a biasing transistor with a source-drain pathway aligned with the DC current path and a gate terminal coupled to a biasing voltage source.

7. The apparatus according to claim 1 further comprising:

the DC current paths in the first and second square wave oscillator branches include a biasing transistor with a source-drain pathway aligned with the DC current path and a gate terminal coupled to a biasing voltage source; and

a biasing resistor coupled between the biasing voltage source and the gate terminal of the biasing transistor in at least one of the DC current paths.

8. The apparatus according to claim 1 further comprising:

the DC current paths in the first and second square wave oscillator branches include a biasing transistor with a source-drain pathway aligned with the DC current path and a gate terminal coupled to a biasing voltage source; and

a capacitor coupled between the gate terminal of the biasing transistor and the second voltage reference.

9. The apparatus according to claim 1 wherein:

the signal current paths in the first and second square wave oscillator branches include a local oscillator transistor having a source-drain pathway aligned with the signal current path and a gate terminal coupled to a square wave oscillator signal and to an inverse of the square wave oscillator signal, respectively, in the first and second square wave oscillator branches.

10. The apparatus according to claim 1 further comprising:

the signal current paths in the first and second square wave oscillator branches include a local oscillator transistor having a source-drain pathway aligned with the signal current path and a gate terminal coupled to a square wave oscillator signal and to an inverse of the square wave oscillator signal, respectively, in the first and second square wave oscillator branches; and

a capacitor coupled on the signal current paths in the first and second square wave oscillator branches in series with the local oscillator transistor.

11. The apparatus according to claim 1 further comprising:

in at least one of the first and second square wave oscillator branches, a load resistor coupled between the first voltage reference and a node coupling the DC current path and the signal current path.

12. The apparatus according to claim 1 further comprising:

in at least one of the first and second square wave oscillator branches, a current source coupled between the first voltage reference and a node coupling the DC current path and the signal current path.

13. The apparatus according to claim 1 further comprising:

in at least one of the first and second square wave oscillator branches, a current source coupled between the first voltage reference and a node coupling the DC current path and the signal current path; and

in at least one of the first and second square wave oscillator branches, an RC filter coupled between the second voltage reference and the node coupling the DC current path and the signal current path.

14. The apparatus according to claim 1 further comprising:

in at least one of the first and second square wave oscillator branches, a current source coupled between the first voltage reference and a node coupling the DC current path and the signal current path;

in at least one of the first and second square wave oscillator branches, an RC filter coupled between the second voltage reference and the node coupling the DC current path and the signal current path; and

a biasing transistor having a source-drain pathway coupled between the RC filter coupled and the node coupling the DC current path and the signal current path.

15. The apparatus according to claim 1 further comprising:

in at least one of the first and second square wave oscillator branches, a current source coupled in parallel with a parasitic capacitor, the current source and parasitic capacitor being coupled between the first voltage reference and a node coupling the DC current path and the signal current path.

16. The apparatus according to claim 1 wherein:

the apparatus is a square wave analog multiplier.

17. The apparatus according to claim 1 wherein:

the apparatus is a square wave analog mixer.

18. A method of processing a signal comprising:

mixing the signal with an oscillating signal, the signal having a signal current flowing in a signal current path;

alternately switching the oscillating signal using a square wave oscillation, the switching operation being made by switches having inherently different switching characteristics that translate to a DC offset current; and

adding a current source in parallel with the signal current path, the current source being in a DC signal path for switching the DC offset current, the signal current path thereby switching only signal current with substantially no switching of DC current.

19. The method according to claim 18 further comprising:

mixing the signal in two branches with the first branch being oscillated by a square wave oscillating signal and the second branch being oscillated by a complementary square wave oscillating signal that is the inverse of the square wave oscillating signal.

20. The method according to claim 18 further comprising:

sourcing a current through the parallel connection of the signal current path and the DC current path.

21. The method according to claim 18 further comprising:

sourcing a current through the parallel connection of the signal current path and the DC current path; and

filtering the parallel connection of the signal current path and the DC current path to remove high frequency components and retain a down-converted signal.

22. A method of processing a signal comprising:

coupling a circuit including a first square wave oscillator branch and a second square wave oscillator branch between a first voltage reference and a second voltage reference;

driving the first square wave oscillator branch using a square wave oscillator signal;

driving the second square wave oscillator branch using an inverse of the square wave oscillator signal; and

separating each of the first and second square wave oscillator branches into a DC current path and a signal current path, the signal current path being driven by the square wave oscillator signal and the inverse of the square wave oscillator signal, respectively, the DC current path carrying a DC current, removing DC offset of signals in the signal current paths.

23. The method according to claim 22 further comprising:

connecting the first and second oscillator branches into a common pathway; and

applying a system input signal to control the current in the common pathway.

24. The method according to claim 22 further comprising:

biasing the current in the common pathway.

25. The method according to claim 24 further comprising:

biasing the currents in the DC current paths in the first and second square wave oscillator branches.

26. The method according to claim 22 further comprising:

sourcing a current to the first square wave oscillator branch and to the second square wave oscillator branch.

27. The method according to claim 22 further comprising:

sourcing a current to the first square wave oscillator branch and to the second square wave oscillator branch; and

filtering signals in the first square wave oscillator branch and the second square wave oscillator branch using an RC filter.

28. The method according to claim 22 further comprising:

sourcing a current to the DC current path and the signal current path in at least one of the first and second square wave oscillator branches;

filtering signals in the DC current path and the signal current path in at least one of the first and second square wave oscillator branches using an RC filter; and

biasing the current in a pathway to the RC filter.

29. The method according to claim 22 further comprising:

coupling a current source coupled in parallel with a parasitic capacitor between a first voltage reference and a node coupling the DC current path and the signal current path in at least one of the first and second square wave oscillator branches.

30. A signal processor comprising:

means for coupling a circuit including a first square wave oscillator branch and a second square wave oscillator branch between a first voltage reference and a second voltage reference;

means for driving the first square wave oscillator branch using a square wave oscillator signal;

means for driving the second square wave oscillator branch using an inverse of the square wave oscillator signal; and

means for separating each of the first and second square wave oscillator branches into a DC current path and a signal current path, the signal current path being driven by the square wave oscillator signal and the inverse of the square wave oscillator signal, respectively, the DC current path carrying a DC current, removing DC offset of signals in the signal current paths.

31. The signal processor according to claim 30 further comprising:

means for connecting the first and second oscillator branches into a common pathway; and

means for applying a system input signal to control the current in the common pathway.

32. The signal processor according to claim 30 further comprising:

means for biasing the current in the common pathway.

33. The signal processor according to claim 32 further comprising:

means for biasing the currents in the DC current paths in the first and second square wave oscillator branches.

34. The signal processor according to claim 30 further comprising:

means for sourcing a current to the first square wave oscillator branch and to the second square wave oscillator branch.

35. The signal processor according to claim 30 further comprising:

means for sourcing a current to the first square wave oscillator branch and to the second square wave oscillator branch; and

means for filtering signals in the first square wave oscillator branch and the second square wave oscillator branch using an RC filter.

36. The signal processor according to claim 30 further comprising:

means for sourcing a current to the DC current path and the signal current path in at least one of the first and second square wave oscillator branches;

means for filtering signals in the DC current path and the signal current path in at least one of the first and second square wave oscillator branches using an RC filter; and

means for biasing the current in a pathway to the RC filter.

37. The signal processor according to claim 30 further comprising:

means for coupling a current source coupled in parallel with a parasitic capacitor between a first voltage reference and a node coupling the DC current path and the signal current path in at least one of the first and second square wave oscillator branches.