Electronics for a shock hardened data recorder

• US 6,560,494 B1
• Filed: 06/02/2000
• Issued: 05/06/2003
• Est. Priority Date: 06/02/2000
• Status: Expired due to Fees

• Current Assignee: The United States of America As Represented By The Secretary of Agriculture
• Original Assignee: the united states of america as represented by the secretary of the navy
• Inventors: Soto, Gabriel H., Haddon, Michael D.
• Primary Examiner(s): Follansbee, John A.
• Assistant Examiner(s): Hartman, Jr., Ronald D
• Application Number:
  US09/585,730
• Time in Patent Office: 1,068 Days
• Field of Search: 700/73, 700/79, 701/14, 361/92, 361/111, 346/38, 702/187
• US Class Current: 700/73
• CPC Class Codes: G05B 19/00 Programme-control systems

Abstract

Electronics for a shock-hardened device, in particular a data recorder, incorporating non-volatile memory. The device has the functional elements: a signal conditioning circuit, an oscillator, an analog-to-digital converter (ADC), a field programmable gate array (FPGA), a trigger, and a non-volatile memory incorporating both electrically erasable programmable read only memory (EEPROM) and fast static random access memory (SRAM). As a recorder, the electronics enable efficient and reliable data recording in extreme shock environments, e.g., those involving dynamic testing of weapons such as target penetrating bombs or dual-stage warheads. It also provides for data retention upon loss or shutdown of power to the unit and yields high mean time between failures (MTBF) figures in more benign environments.

Claims

1. An electronic device, physically protected from shock, comprising:

a signal conditioning circuit, having an input and an output;

said signal-conditioning circuit comprises;

a voltage regulator, having an input and an output;

a first capacitor operably connected to said voltage regulator'"'"'s input;

a second capacitor operably connected to said voltage regulator'"'"'s output;

a diode, operably connected to said voltage regulator'"'"'s input, for reverse voltage protection; and

a surge-suppressing diode imposed between the output of said signal conditioning circuit and an electrical ground,

wherein said signal-conditioning circuit enables provision of filtered and regulated power to said electronic device;

a timing source operably connected to said signal-conditioning circuit;

an analog-to-digital converter (ADC), operably connected to said signal-conditioning circuit;

a trigger for initiating events, operably connected to said signal conditioning circuit, said timing source, and said ADC;

a controller, operably connected to each of said signal conditioning circuit, said ADC, said timing source, and said trigger; and

a non-volatile memory, operably connected to each of said controller and said signal conditioning circuit,

wherein said electronic device acquires data, retains at least portions of said data in said non-volatile memory, and processes said data for output during events subjecting the electronic device to shock, power disruption, or both.

2. An electronic device, physically protected from shock, comprising:

a signal conditioning circuit, having an input and an output;

a timing source operably connected to said signal-conditioning circuit;

an analog-to-digital converter (ADC), operably connected to said signal-conditioning circuit;

a trigger for initiating events, operably connected to said signal conditioning circuit, said timing source, and said ADC;

a controller, operably connected to each of said signal conditioning circuit, said ADC, said timing source, and said trigger; and

a non-volatile memory, operably connected to each of said controller and said signal conditioning circuit,

said non-volatile memory consisting essentially of electronically erasable programmable read only memories (EEPROMs) and fast static random access memories (SRAMs), at least one of each of said EEPROMs and said SRAMs configured on each of a first and second memory chip,

wherein, said non-volatile memory receives input from said controller in the form of two 8-bit bytes, a first 8-bit byte consisting of a most significant byte and a memory address, and a second 8-bit byte consisting of a least significant byte and a memory address, and

wherein said most significant byte is read into said first memory chip and said least significant byte is read into said second memory chip in the order of most significant byte first and least significant byte second;

wherein said electronic device acquires data, retains at least portions of said data in said non-volatile memory, and processes said data for output during events subjecting the electronic device to shock, power disruption, or both.

3. A data recorder, physically operable and survivable during shock, comprising:

a signal conditioning circuit, having an input and an output;

said signal-conditioning circuit comprises;

a voltage regulator, having an input and an output;

a first capacitor operably connected to said voltage regulator'"'"'s input;

a second capacitor operably connected to said voltage regulator'"'"'s output;

a diode, operably connected to said voltage regulator'"'"'s input, for reverse voltage protection; and

a surge-suppressing diode imposed between the output of said signal conditioning circuit and an electrical ground,

wherein said signal-conditioning circuit enables provision of filtered and regulated power to said electronic device;

a timing source operably connected to said signal-conditioning circuit;

an analog-to-digital converter (ADC), operably connected to said signal-conditioning circuit;

a trigger for initiating events, operably connected to said signal conditioning circuit, said timing source, and said ADC;

a controller, operably connected to each of said signal conditioning circuit, said ADC, said timing source, and said trigger; and

a non-volatile memory, operably connected to each of said controller and said signal conditioning circuit,

wherein said electronic device acquires data, retains at least portions of said data in said non-volatile memory, and processes said data for output during-events subjecting the electronic device to shock, power disruption, or both.

4. A data recorder, physically operable and survivable during shock, comprising

a signal conditioning circuit, having an input and an output;

a timing source operably connected to said signal-conditioning circuit;

an analog-to-digital converter (ADC), operably connected to said signal-conditioning circuit;

a trigger for initiating events, operably connected to said signal conditioning circuit, said timing source, and said ADC;

a controller, operably connected to each of said signal conditioning circuit, said ADC, said timing source, and said trigger; and

a non-volatile memory, operably connected to each of said controller and said signal conditioning circuit,

said non-volatile memory consisting essentially of electronically erasable programmable read only memories (EEPROMs) and fast static random access memories (SRAMs), at least one of each of said EEPROMs and said SRAMs configured on each of a first and second memory chip,

wherein, said non-volatile memory receives input from said controller in the form of two 8-bit bytes, a first 8-bit byte consisting of a most significant byte and a memory address, and a second 8-bit byte consisting of a least significant byte and a memory address, and

wherein said most significant byte is read into said first memory chip and said least significant byte is read into said second memory chip in the order of most significant byte first and least significant byte second;

wherein said electronic device acquires data, retains at least portions of said data in said non-volatile memory, and processes said data for output during events subjecting the electronic device to shock, power disruption, or both.