Method and apparatus for measuring on-wafer lumped capacitances in integrated circuits

• US 6,560,567 B1
• Filed: 03/03/1999
• Issued: 05/06/2003
• Est. Priority Date: 03/03/1999
• Status: Expired due to Fees

• Current Assignee: DIE-Soft Corporation
• Original Assignee: DIE-Soft Corporation
• Inventors: Yechuri, Sitaramao S.
• Primary Examiner(s): Broda, Samuel
• Application Number:
  US09/262,129
• Time in Patent Office: 1,525 Days
• Field of Search: 703/1, 703/2, 703/13-28, 702/57, 702/65, 702/75-76, 716/4-7
• US Class Current: 703/2
• CPC Class Codes: G01R 31/2843 In-circuit-testing
• CPC Class Codes: G01R 31/64 Testing of capacitors

Abstract

A novel test structure is described which can be used to accurately measure on-wafer impedances. For example, accurate measurements of the parasitic capacitances inside active devices such as Field Effect Transistors or the capacitance of interconnect lines with either the substrate or with each other can be made. The test technique involves frequency sweep S-parameter power measurements made in the range of 50 MHz to about 20 GHz. One or more identical copies of the DUT are connected on the wafer with one or more on-wafer inductances which are usually lumped, to form a two port circuit. The circuit is essentially a filter operating in the frequency range of 50 MHz to 20 GHz. Although filter circuits are normally designed to provide a flat response in the pass and stop bands, with as sharp a skirt as possible, the objective in designing this test circuit is to design a filter response with sharp inflection points that are uniquely dependent on the reactances that comprise the filter circuit. The primary focus during design is to pre-estimate the impedance (e.g. capacitance) of the DUT, and to design the on-wafer inductances used in the circuit such that the frequency response has sharp peaks and valleys, which are easily identified from measurement. In this way the frequencies of the peaks and valleys can be accurately measured. The measured frequency response is then compared to a model of the circuit.

Claims

1. A method for determining complex impedances of test devices in an integrated circuit chip comprising the steps of:

selecting a first device in a fabricated integrated circuit on a wafer, including parasitic, interelectrode and circuit capacitances and inductances giving rise to a complex impedance for the first device,

estimating a first complex impedance term associated with the first device;

fabricating a circuit on an integrated circuit on the sane wafer, the circuit including the first device as well as circuit impedances with known complex impedance terms,

deriving a mathematical model of the fabricated circuit which represents a theoretical frequency response of the circuit, the mathematical model including the first complex impedance term and the known complex impedance terms;

determining the actual frequency response of the fabricated circuit, and

adjusting the theoretical frequency response and the associated complex impedance terms of the fabricated circuit to fit the actual frequency response of the first device, whereby the first complex impedance term is determined when the theoretical frequency response matches the actual frequency response.

2. A method for determining complex impedances of devices in an integrated circuit chip comprising the steps of:

selecting a first device;

selecting a first complex impedance term associated with the first device;

fabricating a circuit on an integrated circuit chip, the circuit including the first device;

deriving a mathematical model of the circuit which represents a theoretical frequency response of the circuit, the mathematical model including the first complex impedance term;

determining the actual frequency response of the circuit; and

fitting the actual frequency response to the theoretical frequency response, whereby the first complex impedance term is determined when the theoretical frequency response matches the actual frequency response wherein the step of determining the actual frequency response includes making a frequency measurement sweep of the circuit by applying an AC voltage input signal.

3. The method of claim 2 wherein the frequency measurement sweep further includes applying a DC offset voltage to the circuit in addition to the AC voltage input signal repeatedly for a plurality of DC offset voltages.

4. The method of claim 2 further including selecting a second device and incorporating the second device in the circuit.

5. The method of claim 4 wherein the first and second devices have a common terminal connection.

6. The method of claim 2 wherein the first device is an interdigitated capacitor.

7. A method for determining complex impedances of devices in an integrated circuit comprising the steps of:

(a) selecting a first device under test (DUT);

(b) selecting a first instance of the DUT, the first instance of the DUT having a first set of physical dimensions;

(c) fabricating a first circuit on a semiconductor wafer, the first circuit including the first instance of the DUT;

(d) selecting a second instance of the DUT, the second instance of the DUT having a second set of physical dimensions;

(e) fabricating a second circuit on the semiconductor wafer, the second circuit including the second instance of the DUT but otherwise being substantially identical to the first circuit;

(f) deriving a mathematical model representing the first and second circuits, the model including complex impedance terms representative of the DUT;

(g) making a frequency measurement sweep of the first circuit to produce a first actual frequency response plot;

(h) making a frequency measurement sweep of the second circuit to produce a second actual frequency response plot;

(i) fitting the mathematical model to the first actual frequency response plot, thereby producing a first fitted model corresponding to the first device;

(j) fitting the mathematical model to the second actual frequency response plot, thereby producing a second fitted model corresponding to the second device; and

(k) deriving a generalized model based on differences between the first and second fitted model and on differences between the first and second set of physical dimensions, whereby the generalized model represents the complex impedance terms of the DUT as a function of the physical dimensions of the DUT.

8. The method of claim 7 wherein the first and second circuits further include at least one of an inductor, a capacitor, and a resistor in addition to the DUT.

9. The method of claim 7 wherein steps (g) and (h) include applying a DC offset voltage to the first and second circuits;

the method further including repeating steps (g) through (k) using different DC offset voltages.

10. The method of claim 7 wherein the DUT is a transistor.

11. The method of claim 7 wherein the first set of physical dimensions includes a first gate-width dimension and a first gate-length dimension and the second set of physical dimensions includes a second gate-width dimension and a second gate-length dimension.

12. The method of claim 7 wherein the DUT is an interdigitated capacitor.

13. The method of claim 7 wherein the complex impedance terms include capacitance terms.

14. The method of claim 7 wherein the complex impedance terms include inductance terms.

15. The method of claim 7 wherein the complex impedance terms include resistive terms.

16. A method for determining lumped capacitances in an integrated circuit chip comprising the steps of:

selecting a device, the device having a characteristic capacitance;

fabricating a circuit on an integrated circuit chip, the circuit including a first instance of the device and at least one inductor;

determining a first frequency response of the circuit based on a theoretical analysis of the circuit;

making a frequency sweep of the circuit to obtain a second frequency response; and

determining a capacitance value of the first device based on differences between the first and second frequency responses wherein the first and second frequency responses each is represented by S-parameter plots having peaks and valleys, and wherein the step of determining a capacitance value includes comparing the peaks and valleys of the S-parameter plots.

17. The method of claim 16 further including incorporating a second instance of the device in the circuit.

18. The method of claim 17 wherein the first and second instances of the device have a common terminal connection.

19. The method of claim 16 wherein the device is an interdigitated capacitor.

20. A method of determining lumped capacitances in an integrated circuit chip comprising the steps of:

selecting a device under test (DUT);

forming a first circuit on an integrated circuit chip, the first circuit having at least one inductive element and a first instance of the DUT;

selecting a modification to a physical parameter of the DUT;

forming a second circuit on the integrated circuit chip, the second circuit including a second instance of the DUT, the second instance of the DUT having the selected modification, the second circuit being substantially the same as the first circuit otherwise;

determining a model representative of the frequency response of the first and second circuits;

applying test signals to the first and second circuits to collect data representative of actual frequency responses of the circuits; and

determining a mathematical relationship of the capacitance of the DUT as a function of its physical parameters, including;

fitting the model to data corresponding to the first circuit;

fitting the model to data corresponding to the second circuit;

making an analysis of differences between the fitted models and of differences between the physical parameters of the first and second instances of the DUT to produce the mathematical relationship.

21. The method of claim 20 wherein the step of applying test signals includes applying a DC offset voltage to each circuit.

22. The method of claim 21 further including collecting data at a first DC offset voltage and collecting data at a second DC offset voltage;

wherein the step of determining a mathematical relationship is made for the first DC offset voltage and again for the second DC offset voltage.

23. The method of claim 20 wherein the DUT is a transistor and the physical parameter is a gate area of the transistor.

24. The method of claim 20 wherein the DUT is an interdigitated capacitor.