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Method and apparatus for measuring on-wafer lumped capacitances in integrated circuits

  • US 6,560,567 B1
  • Filed: 03/03/1999
  • Issued: 05/06/2003
  • Est. Priority Date: 03/03/1999
  • Status: Expired due to Fees
First Claim
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1. A method for determining complex impedances of test devices in an integrated circuit chip comprising the steps of:

  • selecting a first device in a fabricated integrated circuit on a wafer, including parasitic, interelectrode and circuit capacitances and inductances giving rise to a complex impedance for the first device, estimating a first complex impedance term associated with the first device;

    fabricating a circuit on an integrated circuit on the sane wafer, the circuit including the first device as well as circuit impedances with known complex impedance terms, deriving a mathematical model of the fabricated circuit which represents a theoretical frequency response of the circuit, the mathematical model including the first complex impedance term and the known complex impedance terms;

    determining the actual frequency response of the fabricated circuit, and adjusting the theoretical frequency response and the associated complex impedance terms of the fabricated circuit to fit the actual frequency response of the first device, whereby the first complex impedance term is determined when the theoretical frequency response matches the actual frequency response.

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