System and method for terminating lock-step sequences in a multiprocessor system
First Claim
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1. For use in a processing system containing a plurality of processors coupled to a main memory by a first common bus, a control circuit for breaking a lock-step sequence of memory requests received from said processors, said control circuit comprising:
- a memory request generator coupled to said first common bus for generating an additional memory request separate from the memory requests of the lock-step sequence, the additional memory request having a higher service priority than the memory requests of said lock-step sequence to perturb a timing of said lock-step sequence of memory requests;
a plurality of I/O devices coupled to said main memory by a second common bus and said memory request generator is adapted to be coupled to said second common bus and further generates at least one memory request having a higher service priority than memory requests of a lock-step sequence of said I/O devices on said second common bus operable to terminate said lock-step sequence of memory requests received from said I/O devices; and
wherein the additional memory request on said first common bus and said at least one memory request on said second common bus are generated at different times.
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Abstract
There is provided, for use in a processing system containing a plurality of processors coupled to a main memory, a control circuit for perturbing a lock-step sequence of memory requests received from the processors. The control circuit comprises a memory request generator for generating at least one memory request operable to terminate the lock-step sequence of memory requests.
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Citations
19 Claims
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1. For use in a processing system containing a plurality of processors coupled to a main memory by a first common bus, a control circuit for breaking a lock-step sequence of memory requests received from said processors, said control circuit comprising:
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a memory request generator coupled to said first common bus for generating an additional memory request separate from the memory requests of the lock-step sequence, the additional memory request having a higher service priority than the memory requests of said lock-step sequence to perturb a timing of said lock-step sequence of memory requests;
a plurality of I/O devices coupled to said main memory by a second common bus and said memory request generator is adapted to be coupled to said second common bus and further generates at least one memory request having a higher service priority than memory requests of a lock-step sequence of said I/O devices on said second common bus operable to terminate said lock-step sequence of memory requests received from said I/O devices; and
wherein the additional memory request on said first common bus and said at least one memory request on said second common bus are generated at different times. - View Dependent Claims (2, 3, 4, 5, 6)
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7. For use in a processing system containing a plurality of processors coupled to a main memory by a first common bus, a control circuit for breaking a lock-step sequence of memory requests received from said processors, said control circuit comprising:
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a memory request generator coupled to said first common bus for generating an additional memory request separate from the memory requests of the lock-step sequence, the additional memory request having a higher service priority than the memory requests of said lock-step sequence to perturb a timing of said lock-step sequence of memory requests;
a plurality of I/O devices coupled to said main memory by a second common bus and said memory request generator is adapted to be coupled to said second common bus and further generates at least one memory request having a higher service priority than memory requests of a lock-step sequence of said I/O devices on said second common bus operable to terminate said lock-step sequence of memory requests received from said I/O devices; and
wherein the additional memory request on said first common bus and said at least one memory request on said second common bus are generated simultaneously.
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8. A processing system comprising:
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a plurality of processors;
a main memory;
a memory control device coupled to said plurality of processors by a first common bus and to said main memory to receive memory requests from said plurality of processors and to transfer data between said plurality of processors and said main memory;
a control circuit to break a lock-step sequence of memory request received from said processors, said control circuit comprising a memory request generator coupled to said first common bus for generating an additional memory request separate from the memory requests of the lock-step sequence, the additional memory request having a higher service priority than the memory requests of said lock-step sequence to perturb a timing of said lock-step sequence of memory requests;
a plurality of I/O devices coupled to said memory control device by a second common bus, wherein said memory request generator is coupled to said second common bus and further generates at least one memory request having a higher service priority than memory requests of a lock-step sequence of said I/O devices on said second common bus operable to terminate said lock-step sequence of memory requests received from said I/O devices; and
wherein the additional memory request on said first common bus and said at least one memory request on said second common bus are generated at different times. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A processing system comprising:
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a plurality of processors;
a main memory;
a memory control device coupled to said plurality of processors by a first common bus and to said main memory to receive memory requests from said plurality of processors and to transfer data between said plurality of processors and said main memory;
a control circuit to break a lock-step sequence of memory request received from said processors, said control circuit comprising a memory request generator coupled to said first common bus for generating an additional memory request separate from the memory requests of the lock-step sequence, the additional memory request having a higher service priority than the memory requests of said lock-step sequence to perturb a timing of said lock-step sequence of memory requests;
a plurality of I/O devices coupled to said memory control device by a second common bus, wherein said memory request generator is coupled to said second common bus and further generates at least one memory request having a higher service priority than memory requests of a lock-step sequence of said I/O devices on said second common bus operable to terminate said lock-step sequence of memory requests received from said I/O devices; and
wherein the additional memory request on said first common bus and said at least one memory request on said second common bus are generated simultaneously.
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15. In a processing system containing a plurality of processors coupled to a main memory by a first common bus, a method of terminating a lock-step sequence of memory requests received from the processors, the method comprising:
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generating, by a memory request generator coupled to said first common bus, an additional memory request separate from the memory requests of the lock-step sequence, the additional memory request having a higher service priority than the memory requests of said lock-step sequence to perturb a timing of said lock-step sequence of memory requests;
generating at least one memory request having a higher service priority than memory requests of a lock-step sequence of a plurality of I/O devices on a second common bus, the at least one memory request on the second bus operable to terminate a second lock-step sequence of memory requests received from the I/O devices; and
wherein the additional memory request on said first common bus and said at least one memory request on said second common bus are generated at different times. - View Dependent Claims (16, 17, 18)
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19. In a processing system containing a plurality of processors coupled to a main memory by a first common bus, a method of terminating a lock-step sequence of memory requests received from the processors, the method comprising:
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generating, by a memory request generator coupled to said first common bus, an additional memory request separate from the memory requests of the lock-step sequence, the additional memory request having a higher service priority than the memory requests of said lock-step sequence to perturb a timing of said lock-step sequence of memory requests;
generating at least one memory request having a higher service priority than memory requests of a lock-step sequence of a plurality of I/O devices on a second common bus, the at least one memory request on the second bus operable to terminate a second lock-step sequence of memory requests received from the I/O devices; and
wherein the additional memory request on said first common bus and said at least one memory request on said second common bus are generated simultaneously.
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Specification