Bus arbitration in low power system
First Claim
1. A method of conserving power in a data processing system, the data processing system including a processor and system circuitry coupled to the processor, the processor having a processor core and a processor clock controller coupled to the processor core, the method comprising:
- entering a low power state by the processor and the system circuitry; and
enabling bus arbitration by the processor while the processor core remains in the low power state, wherein enabling comprises;
the processor clock controller providing a processor clock for a first duration during which a bus grant signal is provided to the bus requesting device; and
after the first duration, the processor clock controller holding the processor clock for a second duration during which the bus requesting device executes a bus operation.
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Abstract
Power is conserved in a data processing system that includes a processor core and system circuitry coupled to the processor core. A first method for conserving power includes entering a low power state by the processor and the system circuitry and enabling bus arbitration by the processor while the processor core remains in the low power state. One embodiment further contemplates a method of conserving power by granting bus access to a requesting device and entering a power conservation mode by the processor core in response thereto. Bus operations are then performed while the processor core remains in the power conservation mode. Another embodiment contemplates a method of debugging a data processing system in which a debug state is entered by the processor and the system circuitry and, thereafter, bus arbitration is enabled by the processor while the processor core remains in the debug state.
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Citations
22 Claims
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1. A method of conserving power in a data processing system, the data processing system including a processor and system circuitry coupled to the processor, the processor having a processor core and a processor clock controller coupled to the processor core, the method comprising:
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entering a low power state by the processor and the system circuitry; and
enabling bus arbitration by the processor while the processor core remains in the low power state, wherein enabling comprises;
the processor clock controller providing a processor clock for a first duration during which a bus grant signal is provided to the bus requesting device; and
after the first duration, the processor clock controller holding the processor clock for a second duration during which the bus requesting device executes a bus operation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 18, 19)
in response to the first signal, exiting the low power state by the system circuitry to enable bus operations of the bus requesting device.
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7. The method of claim 6, further comprising:
returning to the low power state by the system circuitry after completion of the bus operations, wherein returning to the low power state requires no software intervention.
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8. The method of claim 1, further comprising:
exiting the low power state by the system circuitry to enable bus operations of the bus requesting device while the processor core remains in the low power state.
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9. The method of claim 8, further comprising:
returning to the low power state by the system circuitry after completion of the bus operations.
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10. The method of claim 9, wherein returning to the low power state by the system circuitry requires no software intervention.
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18. The method of claim 1, wherein the first duration is only as long as necessary for providing the bus grant signal.
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19. The method of claim 18, wherein enabling bus arbitration further comprises sending a first signal to the system controller.
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11. A method of conserving power in a data processing system, the data processing system including a processor core and system circuitry coupled to the processor core, the method comprising:
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granting bus access to a requesting device;
entering a power conservation mode by the processor core responsive to granting the bus access; and
performing a bus operation while the processor core remains in the power conservation mode. - View Dependent Claims (12, 13, 14, 21, 22)
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15. A data processing system comprising:
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a system clock controller coupled to provide a clock signal to a bus requesting device;
an arbitration unit; and
a processor clock controller coupled to the arbitration unit, the system clock controller, and a processor core, the processor clock controller enabling a processor clock to allow the arbitration unit to provide a bus grant to the bus requesting device and disabling the processor clock after providing the bus grant while the bus requesting device performs a bus operation. - View Dependent Claims (16, 17, 20)
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Specification