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Method and apparatus for analyzing a layout using an instance-based representation

  • US 6,560,766 B2
  • Filed: 07/26/2001
  • Issued: 05/06/2003
  • Est. Priority Date: 07/26/2001
  • Status: Active Grant
First Claim
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1. A method for analyzing a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout, comprising:

  • receiving a representation of the layout;

    wherein the representation defines a plurality of nodes that include one or more geometrical features;

    converting the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout;

    wherein each node instance can be further processed without having to consider effects of external factors on the node instance; and

    performing further processing on the instance-based representation by processing each node instance only once, whereby the further processing does not have to be repeated on multiple occurrences of the node instance in the layout.

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