Method and apparatus for analyzing a layout using an instance-based representation

• US 6,560,766 B2
• Filed: 07/26/2001
• Issued: 05/06/2003
• Est. Priority Date: 07/26/2001
• Status: Active Grant

• Current Assignee: Synopsys Merger Holdings LLC (Synopsys Incorporated)
• Original Assignee: Numerical Technologies Inc. (Synopsys Incorporated)
• Inventors: Pierrat, Christophe, Wang, Yao-Ting, Chang, Fang-Cheng, Lin, Chin-hsen
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): Dimyan, Magid Y
• Application Number:
  US09/917,526
• Publication Number:
  US 20030023939A1
• Time in Patent Office: 649 Days
• Field of Search: 716/19, 716/17, 716/21, 716/8, 716/11, 716/4, 716/5
• US Class Current: 716/53
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

One embodiment of the invention provides a system that analyzes a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout. The system operates by receiving a representation of the layout, wherein the representation defines a plurality of nodes that include one or more geometrical features. Next, the system converts the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout, wherein each node instance can be further processed without having to consider effects of external factors on the node instance. The system then performs an further processing on the instance-based representation by processing each node instance only once, whereby the processing does not have to be repeated on multiple occurrences of the node instance in the layout.

Claims

1. A method for analyzing a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout, comprising:

receiving a representation of the layout;

wherein the representation defines a plurality of nodes that include one or more geometrical features;

converting the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout;

wherein each node instance can be further processed without having to consider effects of external factors on the node instance; and

performing further processing on the instance-based representation by processing each node instance only once, whereby the further processing does not have to be repeated on multiple occurrences of the node instance in the layout.

2. The method of claim 1, wherein the layout can define at least one of:

features on the semiconductor chip; and

a mask that is used to create features on the semiconductor chip.

3. The method of claim 1, wherein converting the representation into the instance-based representation involves:

considering how interactions with other nodes affect each node; and

considering how environmental attributes specified in the layout affect each node.

4. The method of claim 1,

wherein the layout includes a hierarchy of nodes;

and

wherein a given node in the hierarchy specifies a geometrical feature that is comprised of lower-level geometrical features that are represented by lower-level nodes that appear under the given node in the hierarchy.

5. The method of claim 4, further comprising collapsing the hierarchy, so that each node in the hierarchy is represented by a node instance that is not affected by higher-level or neighboring nodes in the hierarchy.

6. The method of claim 1, wherein performing the further processing involves performing a die-to-database inspection on the layout by:

performing an initial die-to-database inspection on an image generated from a node instance; and

subsequently performing die-to-die inspections between the image and other images generated from other occurrences of the node instance.

7. The method of claim 1, wherein performing the further processing involves performing verification on the layout to verify that a simulated silicon image of a node conforms to a layout of a node.

8. The method of claim 7, wherein the simulated silicon image of the node is generated by applying optical proximity correction or phase shift masking to the node.

9. The method of claim 1, wherein performing the further processing involves performing proximity effect correction while generating a mask to be used in fabricating the circuit, whereby a correction can be calculated once for a given node instance, and the calculated correction can be applied to other occurrences of the given node instance without having to recalculate the correction.

10. A method for analyzing a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout, comprising:

receiving a representation of the layout;

wherein the representation defines a plurality of nodes that include one or more geometrical features;

converting the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout;

wherein each node instance can be further processed without having to consider effects of external factors on the node instance; and

performing a defect analysis by,

locating defects, and

using the instance-based representation to correlate defects with a specific node instance in order to determine if the specific node instance is prone to defects.

11. The method of claim 10, wherein converting the representation into the instance-based representation involves:

considering how interactions with other nodes affect each node; and

considering how environmental attributes specified in the layout affect each node.

12. The method of claim 10,

wherein the layout includes a hierarchy of nodes;

and

wherein a given node in the hierarchy specifies a geometrical feature that is comprised of lower-level geometrical features that are represented by lower-level nodes that appear under the given node in the hierarchy.

13. A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for analyzing a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout, the method comprising:

receiving a representation of the layout;

wherein the representation defines a plurality of nodes that include one or more geometrical features;

converting the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout;

wherein each node instance can be further processed without having to consider effects of external factors on the node instance; and

performing further processing on the instance-based representation by processing each node instance only once, whereby the processing does not have to be repeated on multiple occurrences of the node instance in the layout.

14. The computer-readable storage medium of claim 13, wherein the layout can define:

features on the semiconductor chip;

or

a mask that is used to create features on the semiconductor chip.

15. The computer-readable storage medium of claim 13, wherein converting the representation into the instance-based representation involves:

considering how interactions with other nodes affect each node; and

considering how environmental attributes specified in the layout affect each node.

16. The computer-readable storage medium of claim 13,

wherein the layout includes a hierarchy of nodes;

and

wherein a given node in the hierarchy specifies a geometrical feature that is comprised of lower-level geometrical features that are represented by lower-level nodes that appear under the given node in the hierarchy.

17. The computer-readable storage medium of claim 16, wherein the method further comprises collapsing the hierarchy, so that each node in the hierarchy is represented by a node instance that is not affected by higher-level or neighboring nodes in the hierarchy.

18. The computer-readable storage medium of claim 13, wherein performing the further processing involves performing a die-to-database inspection on the layout by:

performing an initial die-to-database inspection on an image generated from a node instance; and

subsequently performing die-to-die inspections between the image and other images generated from other occurrences of the node instance.

19. The computer-readable storage medium of claim 13, wherein performing the further processing involves performing verification on the layout to verify that a simulated silicon image of a node conforms to a layout of a node.

20. The computer-readable storage medium of claim 19, wherein the simulated silicon image of the node is generated by applying optical proximity correction or phase shift masking to the node.

21. The computer-readable storage medium of claim 13, wherein performing the further processing involves performing proximity effect correction while generating a mask to be used in fabricating the circuit, whereby a correction can be calculated once for a given node instance, and the calculated correction can be applied to other occurrences of the given node instance without having to recalculate the correction.

22. A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for analyzing a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout, the method comprising:

receiving a representation of the layout;

wherein the representation defines a plurality of nodes that include one or more geometrical features;

converting the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout;

wherein each node instance can be further processed without having to consider effects of external factors on the node instance; and

performing a defect analysis by,

locating defects, and

using the instance-based representation to correlate defects with a specific node instance in order to determine if the specific node instance is prone to defects.

23. The computer-readable storage medium of claim 22, wherein converting the representation into the instance-based representation involves:

considering how interactions with other nodes affect each node; and

considering how environmental attributes specified in the layout affect each node.

24. The computer-readable storage medium of claim 22,

wherein the layout includes a hierarchy of nodes;

and

wherein a given node in the hierarchy specifies a geometrical feature that is comprised of lower-level geometrical features that are represented by lower-level nodes that appear under the given node in the hierarchy.

25. An apparatus that analyzes a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout, the apparatus comprising:

a receiving mechanism that is configured to receive a representation of the layout;

wherein the representation defines a plurality of nodes that include one or more geometrical features;

a conversion mechanism that is configured to convert the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout;

wherein each node instance can be further processed without having to consider effects of external factors on the node instance; and

an processing mechanism that is configured to perform further processing on the instance-based representation by analyzing each node instance only once, whereby the processing does not have to be repeated on multiple occurrences of the node instance in the layout.

26. The apparatus of claim 25, wherein the layout can define:

features on the semiconductor chip;

or

a mask that is used to create features on the semiconductor chip.

27. The apparatus of claim 25, wherein the conversion mechanism is configured to:

consider how interactions with other nodes affect each node; and

to

consider how environmental attributes specified in the layout affect each node.

28. The apparatus of claim 25,

wherein the layout includes a hierarchy of nodes;

and

wherein a given node in the hierarchy specifies a geometrical feature that is comprised of lower-level geometrical features that are represented by lower-level nodes that appear under the given node in the hierarchy.

29. The apparatus of claim 28, further comprising a collapsing mechanism that is configured to collapse the hierarchy, so that each node in the hierarchy is represented by a node instance that is not affected by higher-level or neighboring nodes in the hierarchy.

30. The apparatus of claim 25, wherein the processing mechanism is configured to perform a die-to-database inspection on the layout by:

performing an initial die-to-database inspection on an image generated from a node instance; and

subsequently performing die-to-die inspections between the image and other images generated from other occurrences of the node instance.

31. The apparatus of claim 25, wherein the processing mechanism is configured to perform verification on the layout to verify that a simulated silicon image of a node conforms to a layout of the node.

32. The apparatus of claim 31, wherein the simulated silicon image of the node is generated by applying optical proximity correction or phase shift masking to the node.

33. The apparatus of claim 25, wherein the processing mechanism is configured to perform proximity effect correction while generating a mask to be used in fabricating the circuit, whereby a correction can be calculated once for a given node instance, and the calculated correction can be applied to other occurrences of the given node instance without having to recalculate the correction.

34. An apparatus for analyzing a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout, the apparatus comprising:

a receiving mechanism that is configured to receive a representation of the layout;

wherein the representation defines a plurality of nodes that include one or more geometrical features;

a conversion mechanism that is configured to convert the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout;

wherein each node instance can be further processed without having to consider effects of external factors on the node instance; and

a processing mechanism that is configured to,

locate defects, and to

use the instance-based representation to correlate defects with a specific node instance in order to determine if the specific node instance is prone to defects.

35. The apparatus of claim 34, wherein the conversion mechanism is configured to:

consider how interactions with other nodes affect each node; and

to

consider how environmental attributes specified in the layout affect each node.

36. The apparatus of claim 34,

wherein the layout includes a hierarchy of nodes;

and

wherein a given node in the hierarchy specifies a geometrical feature that is comprised of lower-level geometrical features that are represented by lower-level nodes that appear under the given node in the hierarchy.

37. A method for analyzing a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout, comprising:

receiving a representation of the layout;

wherein the representation defines a plurality of nodes that include one or more geometrical features;

converting the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout; and

performing further processing on the instance-based representation, wherein performing the further processing on multiple occurrences of a node instance involves performing the further processing on the node instance only once, and then applying results of the further processing to other occurrences of the node instance.

38. A method for analyzing a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout, comprising:

generating an instance-based representation of a layout by identifying multiple occurrences of identical node instances in the layout;

wherein the instance-based representation defines a plurality of nodes that include one or more geometrical features;

wherein each node instance can be further processed without having to consider effects of external factors on the node instance; and

performing further processing on the instance-based representation by processing each node instance only once, whereby the processing does not have to be repeated on multiple occurrences of the node instance in the layout.

39. A system that analyzes a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout, the system comprising:

a processor;

a memory;

a receiving mechanism that is configured to receive a representation of the layout;

wherein the representation defines a plurality of nodes that include one or more geometrical features;

a conversion mechanism that is configured to convert the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout;

wherein each node instance can be further processed without having to consider effects of external factors on the node instance; and

an processing mechanism that is configured to perform further processing using the processor on the instance-based representation by analyzing each node instance only once, whereby the processing does not have to be repeated on multiple occurrences of the node instance in the layout.