Method for forming gate

• US 6,562,682 B1
• Filed: 09/12/2002
• Issued: 05/13/2003
• Est. Priority Date: 09/12/2002
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Tseng, Uway, Chen, Ming-Shang, Chiu, Hung-Yu
• Primary Examiner(s): BOOTH, RICHARD A
• Application Number:
  US10/065,031
• Time in Patent Office: 243 Days
• Field of Search: 438/257-267, 438/585, 438/592-594
• US Class Current: 438/257
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure

Abstract

The invention provides a method for forming a semiconductor gate, by forming spacers to isolate the interface between the HDP dielectric layer and the polysilicon gate being exposed, thereby preventing single bit failure resulting from defects at the interface between the HDP dielectric layer and the polysilicon gate. After a cap layer is formed on a conductive structure over the substrate, a HDP dielectric layer is formed exposing the cap layer. A top of the HDP dielectric layer is higher than a top of the first conductive layer. After removing the cap layer to form a recess between the HDP dielectric layer and on the conductive structure, spacers are formed on sidewalls of the recess. Afterwards, a conductive layer is formed and connected to the conductive structure.

Claims

1. A method for forming a semiconductor gate, comprising:

providing a substrate, wherein the substrate has a stacked structure comprising a first conductive layer and a cap layer;

forming a high density plasma (HDP) dielectric layer over the substrate, while the cap layer is exposed, wherein a top of the HDP dielectric layer is higher than a top of the first conductive layer;

removing the cap layer to form a recess between the HDP dielectric layer and on the first conductive layer;

forming an oxide spacer on sidewalls of the recess; and

forming a second conductive layer over the substrate to cover the recess so that the first conductive layer is connected to the second conductive layer.

2. The method as claimed in claim 1, wherein materials for forming the first and the second conductive layers include polysilicon.

3. The method as claimed in claim 1, wherein materials for forming the cap layer includes silicon nitride.

4. The method as claimed in claim 3, wherein removing the cap layer comprises using hot phosphoric acid.

5. The method as claimed in claim 1, wherein the HDP dielectric layer includes a HDP oxide layer.

6. The method as claimed in claim 5, wherein forming the HDP dielectric layer comprises:

forming a HDP oxide layer over the substrate to cover the cap layer; and

using HF to remove a portion of the HDP oxide layer to expose the cap layer.

7. A method for forming a floating gate for a flash memory, comprising:

providing a substrate, wherein the substrate has a stacked structure comprising a first conductive layer and a cap layer;

forming a high density plasma (HDP) dielectric layer over the substrate, while the cap layer is exposed, wherein a top of the HDP dielectric layer is higher than a top of the first conductive layer;

removing the cap layer to form a recess between the HDP dielectric layer and on the first conductive layer;

forming an oxide layer to cover the recess;

defining the oxide layer to expose the cap layer, leaving a portion of the oxide layer on sidewalls of the recess; and

forming a second conductive layer over the substrate to cover the recess so that the first conductive layer is connected to the second conductive layer.

8. The method as claimed in claim 7, further comprising defining the second conductive layer to form a plurality of floating gates after forming the second conductive layer.

9. The method as claimed in claim 7, wherein materials for forming the first and the second conductive layers include polysilicon.

10. The method as claimed in claim 7, wherein materials for forming the cap layer includes silicon nitride.

11. The method as claimed in claim 10, wherein removing the cap layer comprises using hot phosphoric acid.

12. The method as claimed in claim 7, wherein the HDP dielectric layer includes a HDP oxide layer.

13. The method as claimed in claim 12, wherein forming the HDP dielectric layer comprises:

forming a HDP oxide layer over the substrate to cover the cap layer; and

using HF to remove a portion of the HDP oxide layer to expose the cap layer.

14. A method for forming a floating gate for a flash memory, comprising:

forming a conductive structure on a substrate;

forming a cap layer on the conductive structure;

forming a high density plasma (HDP) dielectric layer over the substrate, while the cap layer is exposed, wherein a top of the HDP dielectric layer is higher than a top of the conductive structure;

removing the cap layer to form a recess between the HDP dielectric layer and on the conductive structure;

forming an oxide spacer on sidewalls of the recess; and

forming a conductive layer over the substrate to cover the recess so that the conductive structure is connected to the conductive layer.

15. The method as claimed in claim 14, further comprising defining the conductive layer to form a plurality of floating gates after forming the conductive layer.

16. The method as claimed in claim 14, wherein materials for forming the conductive structure and the conductive layer include polysilicon.

17. The method as claimed in claim 14, wherein forming the oxide spacer on sidewalls of the recess comprises:

forming an oxide layer over the substrate; and

performing etching back to the oxide layer.

18. The method as claimed in claim 14, wherein the HDP dielectric layer includes a HDP oxide layer.

19. The method as claimed in claim 14, wherein materials for forming the cap layer includes silicon nitride.

20. The method as claimed in claim 19, wherein removing the cap layer comprises using hot phosphoric acid.