Method of reducing capacitance of interconnect

• US 6,562,711 B1
• Filed: 06/28/2002
• Issued: 05/13/2003
• Est. Priority Date: 06/28/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Powers, James
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): GURLEY, LYNNE ANN
• Application Number:
  US10/186,072
• Time in Patent Office: 319 Days
• Field of Search: 438/622, 438/629, 438/634, 438/672, 438/675
• US Class Current: 438/622
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention discloses a method of providing a substrate, the substrate having a first metal line and a second metal line isolated horizontally by a dielectric; forming an etch stop layer over the substrate; reducing thickness of the etch stop layer over the first metal line, leaving thickness unchanged over the second metal line; forming an interlayer dielectric (ILD) over the etch stop layer; and removing the ILD over the second metal line.

The present invention further discloses a structure that includes a substrate; a first metal line and a second metal line located over the substrate; a dielectric located over the substrate adjacent to the first metal line and the second metal line; an etch stop layer located over the first metal line, the second metal line, and the dielectric, the etch stop layer being thicker over the second metal line; and a via located over the thicker etch stop layer over the second metal line.

Claims

1. A method comprising:

providing a substrate, said substrate having a first metal line and a second metal line isolated by a dielectric;

forming an etch stop layer over said substrate;

partially reducing thickness of said etch stop layer over said first metal line, leaving thickness unchanged over said second metal line;

forming an interlayer dielectric (ILD) over said etch stop layer; and

removing said ILD over said second metal line.

2. The method of claim 1 wherein said ILD comprises a Silicon Oxide.

3. The method of claim 1 wherein said ILD comprises a low-k material.

4. The method of claim 1 wherein said ILD comprises an ultra-low k material.

5. The method of claim 1 wherein said first metal line and said second metal line comprise Copper.

6. The method of claim 1 wherein said etch stop layer comprises Silicon Nitride.

7. The method of claim 1 wherein said etch stop layer comprises Silicon Carbide.

8. The method of claim 1 wherein said etch stop layer over said first metal line is reduced in thickness from about 100.0 nm to about 30.0 nm.

9. A method comprising:

providing a substrate, said substrate having a first metal line and a second metal line isolated by a dielectric;

forming an etch stop layer over said first metal line and said second metal line;

forming a landing pad over said second metal line by partially etching said etch stop layer outside said landing pad, including over said first metal line;

forming an interlayer dielectric (ILD) over said etch stop layer; and

etching a via in said ILD down to said landing pad.

10. The method of claim 9 wherein partially etching said etch stop layer outside said landing pad may decrease dielectric constant, k, value of a dielectric stack over said first metal line by about 10.0%.