Non-volatile semiconductor memory device and method for producing the same
First Claim
1. A non-volatile semiconductor memory device, comprising:
- a semiconductor substrate;
memory cells;
a region of memory cell array in which said memory cells are arranged in a matrix-like form;
a region of peripheral circuit;
a connecting region connecting said region of memory cell array to said region of peripheral circuit; and
lowest conductive layers provided over said substrate with intervals between each other, wherein said interval of said lowest conductive layers in said region of memory cell array is substantially equal to said interval of said lowest conductive layers in said connecting region, and two diffusion regions are continuously formed between said lowest conductive layers in said region of memory cell array and said connecting region while interposing an isolation region between said two diffusion regions.
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Abstract
A non-volatile semiconductor memory device comprising: a semiconductor substrate, memory cells, a region of memory cell array in which said memory cells are arranged in a matrix-like form, a region of peripheral circuit, a connecting region for connecting said region of memory cell array to said region of peripheral circuit, and conductive layers provided closest to said substrate with intervals between each other, wherein said intervals of said conductive layers are substantially equal to each other in said region of memory cell array and said connecting region, whereby when insulating films are formed and planarized after forming said conductive layers, it is possible to restrict producing of seams in the insulating films at stripped portions of the conductive layers.
8 Citations
3 Claims
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1. A non-volatile semiconductor memory device, comprising:
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a semiconductor substrate;
memory cells;
a region of memory cell array in which said memory cells are arranged in a matrix-like form;
a region of peripheral circuit;
a connecting region connecting said region of memory cell array to said region of peripheral circuit; and
lowest conductive layers provided over said substrate with intervals between each other, wherein said interval of said lowest conductive layers in said region of memory cell array is substantially equal to said interval of said lowest conductive layers in said connecting region, and two diffusion regions are continuously formed between said lowest conductive layers in said region of memory cell array and said connecting region while interposing an isolation region between said two diffusion regions. - View Dependent Claims (2, 3)
said intervals are 0.5 μ - m or more.
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3. The non-volatile semiconductor memory device according to claim 1, further comprising:
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an insulating film on said diffusion regions and said isolation regions and between said lowest conductive layers; and
second conductive layers in contact with upper sides of said insulating film and respectively on the lowest conductive layers.
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Specification
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- Resources
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Current AssigneeMitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
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Original AssigneeMitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
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InventorsSakakibara, Kiyohiko, Kuriyama, Hirotada
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Primary Examiner(s)CRANE, SARA W
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Application NumberUS09/199,264Publication NumberTime in Patent Office1,630 DaysField of Search257/315, 257/316, 365/185.01, 365/185.06, 365/185.33US Class Current257/315CPC Class CodesH01L 29/42324 Gate electrodes for transis...H10B 41/30 characterised by the memory...H10B 41/40 characterised by the periph...H10B 41/42 Simultaneous manufacture of...H10B 69/00 Erasable-and-programmable R...
