Non-volatile semiconductor device with anti-punch through regions

• US 6,563,168 B2
• Filed: 11/21/2001
• Issued: 05/13/2003
• Est. Priority Date: 07/10/1998
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Yong-Kyu
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): Weiss, Howard
• Application Number:
  US09/989,113
• Publication Number:
  US 20020052080A1
• Time in Patent Office: 538 Days
• Field of Search: 257/316, 257/326
• US Class Current: 257/316
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/48 with a tunnel dielectric layer also being used as part of the peripheral transistor
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor

Abstract

A non-volatile semiconductor device and a method of making such a device having a memory cell formation part and a peripheral circuit part having high and low-voltage transistor formation parts, wherein the device includes an anti-punch through region surrounding a drain region in the memory cell formation part, and surrounding drain and source regions of the low-voltage transistor formation part.

Claims

1. A non-volatile semiconductor device comprising:

a substrate;

a memory cell formation part disposed on a predetermined part of the substrate, the memory cell formation part comprising at least a drain region, a first lightly doped drain region, a second lightly doped drain region, a source region, a floating gate and a word line;

a peripheral circuit part disposed on a predetermined part of the substrate, the peripheral circuit part comprising a high-voltage transistor formation part and a low-voltage transistor formation part wherein the high-voltage transistor formation part comprises at least a source region, a drain region, a first lightly doped drain region and a gate region with sidewall spacers and the low-voltage transistor formation part comprises at least a source region, a drain region, a third lightly doped drain region and a gate region with sidewall spacers; and

anti-punch through regions surrounding only;

(a) the drain and the second lightly doped drain regions of the memory cell formation part; and

(b) the drain, the source and the third lightly doped drain regions of the low-voltage transistor formation part.

2. The device as claimed in claim 1, wherein the anti-punch through regions, the drain and the second lightly doped drain regions of the memory cell formation part, the source, the drain and the first lightly doped drain regions of the high-voltage transistor formation part and the source, the drain and the third lightly doped drain regions of the low-voltage transistor formation part are each doped with impurity ions, wherein the impurity ions of the anti-punch through regions are of a type opposite to that of the source, the drain and the first, second and third lightly doped drain regions.