Three dimensional structure integrated circuit

• US 6,563,224 B2
• Filed: 05/15/2002
• Issued: 05/13/2003
• Est. Priority Date: 04/04/1997
• Status: Expired due to Term

• Current Assignee: Elm 3DS Innovations LLC
• Original Assignee: ELM TECHNOLOGY CORPORATION
• Inventors: Leedy, Glenn J.
• Primary Examiner(s): Meier, Stephen D.
• Application Number:
  US10/144,791
• Publication Number:
  US 20020135075A1
• Time in Patent Office: 363 Days
• Field of Search: 257/778, 257/777
• US Class Current: 257/778
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/8083 Solid-solid interdiffusion
• CPC Class Codes: H01L 2224/8384 Sintering
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/02 Semiconductor bodies ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density interlayer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Claims

1. An integrated circuit memory structure comprising:

a first substrate; and

a second substrate bonded to the first substrate to form conductive paths between the first substrate and the second substrate, wherein the second substrate is a thinned substrate having circuitry formed thereon.

2. The apparatus of claim 1, wherein the second substrate is one of a thinned monocrystalline semiconductor substrate and a thinned polycrystalline semiconductor substrate.

3. The apparatus of claim 1, wherein the circuitry formed on the second substrate is one of active circuitry and passive circuitry.

4. The apparatus of claim 1, wherein the circuitry formed on the second substrate consists of both active circuitry and passive circuitry.