Switched capacitor array circuit for use in DC-DC converter and method

• US 6,563,235 B1
• Filed: 10/03/2000
• Issued: 05/13/2003
• Est. Priority Date: 10/03/2000
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: McIntyre, William J., Kotowski, Jeffrey P.
• Primary Examiner(s): FLEMING, FRITZ M
• Application Number:
  US09/678,035
• Time in Patent Office: 952 Days
• Field of Search: 307/109, 307/110
• US Class Current: 307/109
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps

Abstract

A capacitor array circuit having at least two capacitors, switching circuitry coupled to the capacitors and to input, output and common nodes and control circuitry. The control circuitry operates to sequentially switch the array through three different states so that a voltage is developed across each of the capacitors which is at a fixed value proportional to a voltage present at the input node. The fixed and thus determinate voltage drop across each of the capacitors operates to define voltages at any nodes intermediate the capacitors thereby, among other things, insuring reliable operation of the capacitor array circuit.

Claims

1. A capacitor array circuit connected to an input node, an output node and a third node, said capacitor array circuit comprising:

first and second capacitors, with each capacitor having first and second terminals;

switching circuitry coupled to the first and second capacitors and to the input, output and third node;

control circuitry coupled to the switching circuitry and operative to sequentially switch the array circuit through at least three different states so that a voltage developed across each of the first and second capacitors is a fixed proportion of a voltage at the input, node, so that the array circuit has a fixed gain when switched through the at least three different states, so that at least one of the first and second capacitors is connected intermediate two of the input, output and third nodes in each of the three states and so that each of the first and second capacitors has a connection relative to the input, output and third node which changes in at least one of the three states and wherein in at least one of the at least three different states, none of the first and second capacitors is connected between the input and output nodes.

2. The capacitor array circuit of claim 1 wherein the control circuitry operates to switch the array circuit to the first state with the first and second capacitors being connected in series between two of the nodes, to the second state where the first capacitor is connected between two of the nodes and the third state where the second capacitor is connected between two of the nodes.

3. The capacitor array circuit of claim 2 wherein in the first state, one of the two nodes is the third node and wherein in the second and third states, the two nodes are the input and output nodes.

4. The capacitor array circuit of claim 3 wherein in the first state, the two nodes are the input and third nodes.

5. The capacitor array circuit of claim 4 wherein the first terminals of the first and second capacitors are facing the input node in the first, second and third states.

6. The capacitor array circuit of claim 4 where the first terminals of the first and second capacitors are facing the third node in the first state and are facing the input node in the second and third states.

7. The capacitor array circuit of claim 3 wherein in the first state, the two nodes are the output and the third node.

8. The capacitor array circuit of claim 7 wherein the first terminals of the first and second capacitors are facing the output node in the first state and are facing the input nodes in the second and third states.

9. The capacitor array circuit of claim 7 wherein the first terminals of the first and second capacitors are facing the third node in the first state and are facing the input node in the second and third states.

10. The capacitor array circuit of claim 2 wherein in the first, second and third states, one of the two nodes is the third node.

11. The capacitor array circuit of claim 10 wherein in the first state, the first and second capacitors are connected in series between the output node and the third node, in the second state the first capacitor is connected between the input node and the third node and in the third state the second capacitor is connected between the input node and the third node.

12. The capacitor array circuit of claim 11 wherein the first terminals of the first and second capacitors are facing the output node in the first state and wherein the first terminals of the first and second capacitors are facing the input node in the second and third states.

13. The capacitor array circuit of claim 11 wherein the first terminals of the first and second capacitors are facing the third node in the first state and wherein the first terminals of the first and second capacitors are facing the input node in the second and third states.

14. The capacitor array circuit of claim 10 wherein in the first state, the first and second capacitors are connected in series between the input node and the third node, in the second state the first capacitor is connected between the output node and the third node and in the third state the second capacitor is connected between the output node and the third node.

15. The capacitor array circuit of claim 14 wherein in the first state, the first terminal of the first and second capacitors is facing the input node and in the second and third state, the first terminal of the first and second capacitor is facing the output node.

16. The capacitor array circuit of claim 14 wherein in the first state, the first terminal of the first and second capacitors is facing the third node and in the second and third state, the first terminal of the first and second capacitor is facing the output node.

17. The capacitor array circuit of claim 2 further including a third capacitor coupled to the switching circuitry, with the control circuitry operating to switch the array circuit through the at least three different states so that a voltage developed across the third capacitor is a fixed proportion of a voltage at the input node, with the first, second and third capacitors being connected in series between the two of the nodes in the first state and wherein in at least one of the first, second and third states, none of the first, second and third capacitors is connected between the input and the output nodes.

18. The capacitor array circuit of claim 17 wherein the third capacitor is connected in parallel with the first capacitor between two of the nodes in the second state and the second capacitor is connected between two of the nodes in the third state.

19. The capacitor array circuit of claim 18 wherein one of the nodes in the first state is the third node, one of the nodes in the second state is the third node and one of the nodes in the third state is the third node.

20. The capacitor array circuit of claim 19 wherein one of the nodes in the first state is the input node and one of the nodes in the second state is the output node and one of the nodes in the third state is the output node.

21. The capacitor array circuit of claim 19 wherein one of the nodes in the first state is the output node and one of the nodes in the second state is the input node and one of the nodes in the third state is the input node.

22. The capacitor array circuit of claim 2 further including a third capacitor coupled to the switching circuitry and having first and second terminals and wherein the control circuitry is operative to sequentially switch the array circuit through at least four different states so that a voltage is developed across each of the first, second and third capacitors that is a fixed proportion of a voltage at the input node.

23. The capacitor array circuit of claim 22, wherein in the first state one of the two nodes is the third node and the second one of the nodes of the second, third and fourth states is the third node.

24. The capacitor array of claim 23 wherein in the first state one of the two nodes is the third node and the second one of the nodes of the second, third and fourth states is the third node.

25. The capacitor array circuit of claim 24 wherein in the first state another of the two nodes is the input node and the first one of the nodes in the second, third and fourth states is the output node.

26. The capacitor array circuit of claim 25 wherein in the first state, the first terminals of the first, second and third capacitors are facing the input node and in the second, third and fourth states, the first terminals of the first, second and third capacitors are facing the third node.

27. The capacitor array circuit of claim 25 wherein in the first state, the first terminals of the first, second and third capacitors are facing the input node and in the second, third and fourth states, the first terminals of the first, second and third capacitors are facing the output node.

28. The capacitor array circuit of claim 23 wherein in the first state, the two of the nodes are the input and output nodes and wherein the first one of the nodes of the second, third and fourth states are one of the input and output nodes and the second one of the nodes of the second, third and fourth states are the third nodes.

29. The capacitor array circuit of claim 28 wherein the one of the input and output nodes of the second, third and fourth states is the output node.

30. The capacitor array circuit of claim 29 wherein the first terminals of the first, second and third capacitors are facing the input node in the first state and are facing the output node in the second, third and fourth states.

31. The capacitor array circuit of claim 28 wherein the one of the input and output nodes of the second, third and fourth states is the input node.

32. The capacitor array circuit of claim 31 wherein the first terminals of the first, second and third capacitors are facing the input node in the first state and are facing the third node in the second, third and fourth states.

33. The capacitor array circuit of claim 23 wherein in the second state, the first and second capacitors are connected in series between the first and second ones of the nodes, in the third state the second and third capacitors are connected in series between the first and second ones of nodes and in the fourth state the third and first capacitors are connected in series between the first and second ones of the nodes.

34. The capacitor array circuit of claim 33 wherein in the first state, the two of the nodes are the input and output nodes and wherein the first one of the nodes of the second, third and fourth states are one of the input and output nodes and the second one of the nodes of the second, third and fourth states are the third nodes.

35. The capacitor circuit of claim 34 wherein the one of the input and output nodes of the second, third and fourth states is the output node.

36. The capacitor array circuit of claim 35 wherein the first terminals of the first, second and third capacitors are facing the input node in the first state and are facing the output node in the second, third and fourth states.

37. The capacitor array circuit of claim 34 wherein the one of the input and output nodes of the second, third and fourth states is the input node.

38. The capacitor array circuit of claim 37 wherein the first terminals of the first, second and third capacitors are facing the input node in the first state and are facing the third node in the second, third and fourth states.

39. The capacitor array circuit of claim 33 wherein in the first state one of the two nodes is the third node and wherein in the second, third and fourth states the first one of the nodes is the input node and the second one of the nodes is the output node.

40. The capacitor array circuit of claim 39 wherein in the first state one of the two nodes is the input node.

41. The capacitor array circuit of claim 40 wherein the first terminals of the first, second and third capacitors are facing the input node in the first state and are facing the output node in the second, third and fourth states.

42. The capacitor array circuit of claim 40 wherein the first terminals of the first, second and third capacitors are facing the input node in the first state and are facing the input node in the second, third and fourth states.

43. The capacitor array circuit of claim 39 wherein in the first state one of the two nodes is the output node.

44. The capacitor array circuit of claim 43 wherein the first terminals of the first, second and third capacitors are facing the output node in the first state and are facing the input node in the second, third and fourth states.

45. The capacitor array circuit of claim 33 wherein in the first state, the two of the nodes are the input and third nodes and wherein the first one of the nodes of the second, third and fourth states are the output node and the second one of the nodes of the second, third and fourth states are the third node.

46. The capacitor array circuit of claim 45 wherein the first terminals of the first, second and third capacitors are facing the input node in the first state and are facing the third node in the second, third and fourth states.

47. The capacitor array circuit of claim 23 wherein in the first state one of the two nodes is the third node and in the second, third and fourth states, the first and second ones of the nodes are the input and output nodes, respectively.

48. The capacitor array circuit of claim 47 wherein in the first state another of the two nodes is the output node.

49. The capacitor array circuit of claim 48 wherein the first terminals of the first, second and third capacitors are facing the output node in the first state and are facing the input node in the second, third and fourth states.

50. The capacitor array circuit of claim 47 wherein in the first state another of the two nodes is the input node.

51. The capacitor array circuit of claim 50 wherein the first terminals of the first, second and third capacitors are facing the input node in the first state and are facing the output node in the second, third and fourth states.

52. The capacitor circuit of claim 22 wherein in the first state, the first and second capacitors are connected in series between first and second ones of the nodes, in the second state the third capacitor is connected between the first and second ones of the nodes, in the third state, the first and third capacitors are connected in series between third and fourth ones of the nodes and in the fourth state the second and third ones of the capacitors are connected in series between the third and fourth ones of the nodes.

53. The capacitor array circuit of claim 52 wherein the first and second ones of the nodes in the first and second states are the output and third node, respectively, and the third and fourth ones of the nodes in the third and fourth states are the input and output nodes, respectively.

54. The capacitor array circuit of claim 53 wherein the first terminals of the first, second and third capacitors are facing the output node in the first and second states and are facing the input node in the third and fourth states.

55. The capacitor array circuit of claim 52 wherein the first and second ones of the nodes in the first and second states are the input and third node, respectively, and the third and fourth ones of the nodes in the third and fourth states are the output and third nodes, respectively.

56. The capacitor array circuit of claim 55 wherein the first terminals of the first, second and third capacitors are facing the input node in the first and second states and are facing the output node in the third and fourth states.

57. The capacitor array circuit of claim 52 wherein the first and second ones of the nodes in the first and second states are the input and third node, respectively, and the third and fourth ones of the nodes in the third and fourth states are the input and output nodes, respectively.

58. The capacitor array circuit of claim 57 wherein the first terminals of the first, second and third capacitors are facing the input node in the first and second states and are facing the output node in the third and fourth states.

59. A capacitor array circuit connected to an input node, an output node and a third node, said capacitor array circuit comprising:

first and second capacitors, with each capacitor having first and second terminals;

switching circuitry coupled to the first and second capacitors and to the input, output and third node;

control circuitry operative to sequentially switch the array circuit through first, second and third different states, wherein in the first state the first and second capacitors are connected in series between two of the nodes, in the second state, the first capacitor is connected between two of the nodes and in the third state the second capacitor is connected between two of the nodes and wherein the array circuit has a fixed gain when the array circuit is switched through the first, second and third states and in at least one of the first, second and third states, none of the first and second capacitors is connected between the input and output nodes.

60. The capacitor array circuit of claim 59 wherein the first and second capacitors are connected between the input and output nodes in the first state and the first capacitor is connected between input and output nodes in the second state and the second capacitor is connected between the input and output nodes in the third state.

61. The capacitor array circuit of claim 60 wherein the first terminals of the first and second capacitors are facing the input node in the first state and are facing the output node in the second and third state.

62. The capacitor array circuit of claim 60 wherein the first terminals of the first and second capacitors are facing the input node in the first state and are facing the input node in the second and third state.

63. The capacitor array circuit of claim 60 wherein the first terminals of the first and second capacitors are facing the input node in the first state and are facing the output node in the second and third state.

64. The capacitor array circuit of claim 59 wherein the first and second capacitors are connected between the input and third nodes in the first state, the first capacitor is connected between the output and third nodes in the second state and the second capacitor is connected between the output and third nodes in the third state.

65. The capacitor array circuit of claim 64 wherein the first terminals of the first and second capacitors are facing the input node in the first state and are facing the output node in the second and third state.

66. The capacitor array circuit of claim 64 wherein the first terminals of the first and second capacitors are facing the input node in the first state and are facing the third node in the second and third state.

67. The capacitor array circuit of claim 59 wherein the first and second capacitors are connected between the input and third nodes in the first state, the first capacitor is connected between the input and output nodes in the second state and the second capacitor is connected between the input and output nodes in the third state.

68. The capacitor array circuit of claim 67 wherein the first terminals of the first and second capacitors are facing the output node in the first state and are facing the input node in the second and third state.

69. The capacitor array circuit of claim 59 further including a third capacitor having first and second terminals and coupled to the switching circuitry and wherein the control circuitry is operative to sequentially switch the array circuit through first, second, third and fourth states, wherein in the first state the first, second and third capacitors are connected in series between two of the nodes, in the second state the first capacitor is connected between two of the nodes, in the third state the second capacitor is connected between two of the nodes and in the fourth state the third capacitor is connected between two of the nodes and wherein in at least one of the first, second, third and fourth states, none of the first, second and third capacitors is connected between the input and output nodes.

70. The capacitor array circuit of claim 69 wherein the first, second and third capacitors are connected between the input and the third nodes in the first state and the first, second and third capacitors are connected between the output and third nodes in the second, third and fourth states, respectively.

71. The capacitor array circuit of claim 70 wherein the first terminals of the first, second and third capacitors are facing the input node in the first state and are facing the third node in the second, third and fourth states.

72. The capacitor array circuit of claim 70 wherein the first terminals of the first, second and third capacitors are facing the input node in the first state and are facing the output node in the second, third and fourth states.

73. The capacitor array circuit of claim 70 wherein the first and second capacitors are connected in series between the output and third nodes in the second state, the second and third capacitors are connected in series between the output and third nodes in the third state and the third and first capacitors are connected between the output and the third nodes in the fourth state.

74. The capacitor array circuit of claim 73 wherein the first terminals of the first, second and third capacitors are facing the input node in the first state and are facing the output node in the second, third and fourth states.

75. The capacitor array circuit of claim 69 wherein the first, second and third capacitors are connected between the output and third nodes in the first state and first, second and third capacitors are connected between the input and output nodes in the second, third and fourth states, respectively.

76. The capacitor array circuit of claim 75 wherein the first terminals of the first, second and third capacitors are facing the output node in the first state and are facing the input node in the second, third and fourth states.

77. The capacitor array circuit of claim 69 wherein in the second state the first and second capacitors are connected in series between two of the nodes, in the third state the second and third capacitors are connected in series between two of the nodes and in the fourth state the third and first capacitors are connected in series between two of the nodes.

78. The capacitor array circuit of claim 77 wherein the first, second and third capacitors are connected between the input and third nodes in the first state, the first and second capacitor are connected between the input and output nodes in the second state, the second and third capacitors are connected between the input and output nodes in the third state and the third and first capacitors are connected between the input and output nodes in the fourth state.

79. The capacitor array circuit of claim 78 wherein the first terminals of the first, second and third capacitors are facing the input node in the first state and are facing the output node in the second, third and fourth states.

80. The capacitor array circuit of claim 78 wherein the first terminals of the first, second and third capacitors are facing the input node in the first state and are facing the input node in the second, third and fourth states.

81. The capacitor array circuit of claim 77 wherein the first, second and third capacitors are connected between the output and third nodes in the first state, the first and second capacitor are connected between the input and output nodes in the second state, the second and third capacitors are connected between the input and output nodes in the third state and the third and first capacitors are connected between the input and output nodes in the fourth state.

82. The capacitor array circuit of claim 81 wherein the first terminals of the first, second and third capacitors are facing the output node in the first state and facing the input node in the second, third and fourth states.

83. The capacitor array circuit of claim 77 wherein the first, second and third capacitors are connected between the input and third nodes in the first state, the first and second capacitor are connected between the output and third nodes in the second state, the second and third capacitors are connected between the output and third nodes in the third state and the third and first capacitors are connected between the output and third nodes in the fourth state.

84. The capacitor array circuit of claim 83 wherein the first terminals of the first, second and third capacitors are facing the input node in the first state and are facing third node in the second, third and fourth states.

85. The capacitor array circuit of claim 77 wherein the first, second and third capacitors are connected between the input and output nodes in the first state, the first and second capacitor are connected between the output and third nodes in the second state, the second and third capacitors are connected between the output and third nodes in the third state and the third and first capacitors are connected between the output and third nodes in the fourth state.

86. The capacitor array circuit of claim 85 wherein the first terminals of the first, second and third capacitors are facing the input node in the first state and are facing the output node in the second, third and fourth states.

87. The capacitor array circuit of claim 77 wherein the first, second and third capacitors are connected between the input and output nodes in the first state, the first and second capacitor are connected between the input and third nodes in the second state, the second and third capacitors are connected between the input and third nodes in the third state and the third and first capacitors are connected between the input and third nodes in the fourth state.

88. The capacitor array circuit of claim 87 wherein the first terminals of the first, second and third capacitors are facing the output node in the first state and are facing the input node in the second, third and fourth states.

89. The capacitor array circuit of claim 59 further including a third capacitor having first and second terminals and coupled to the switching circuitry and wherein the control circuitry is operative to sequentially switch the array circuit through first, second, third and fourth states, wherein in the first state the first and second capacitors are connected in series between two of the nodes, in the second state the third capacitor is connected between two of the nodes, in the third state the first and third capacitors are connected in series between two of the nodes and in the fourth state the second and third capacitors are connected between two of the nodes.

90. The capacitor array circuit of claim 89 wherein in first state the first and second capacitors are connected between the input and third nodes, in the second state the third capacitor is connected between the input and third nodes, in the third state the first and second capacitors are connected between the output and third nodes and in the fourth state the second and third capacitors are connected between the output and third nodes.

91. The capacitor array circuit of claim 90 wherein the first terminals of the first, second and third capacitors are facing the input node in the first and second stages and are facing the third node in the third and fourth states.

92. The capacitor array circuit of claim 89 wherein in first state the first and second capacitors are connected between the input and third nodes, in the second state the third capacitor is connected between the input and third nodes, in the third state the first and second capacitors are connected between the input and output nodes and in the fourth state the second and third capacitors are connected between the input and output nodes.

93. The capacitor array circuit of claim 92 wherein the first terminals of the first, second and third capacitors are facing the input node in the first and second states and are facing the output node in the third and fourth state.

94. The capacitor array circuit of claim 59 further including a third capacitor having first and second terminals and coupled to the switching circuitry and wherein the control circuitry is operative to sequentially switch the array circuit through first, second and third states, wherein in the first state the first, second and third capacitors are connected in series between two of the nodes, in the second state the first and second capacitors are connected in parallel between two of the nodes and in the third state the third capacitor is connected between two of the nodes and wherein in at least one of the first, second and third states, none of the first, second and third capacitors is connected between the input and output nodes.

95. The capacitor array circuit of claim 94 wherein the first, second and third capacitors are connected in series between one of the input and output nodes and the third node in the first state, the first and second capacitors are connected in parallel between one of the input and output nodes and the third node in the second state and the third capacitor is connected between one of the input and output nodes and the third node in the third state.

96. The capacitor of claim 95 wherein in the first state the one of the input and output nodes is the output node and in the second and third states the one of the input and output nodes is the input node.

97. The capacitor of claim 96 wherein the first terminals of the first, second and third capacitors are facing the output node in the first state and are facing the input nodes in the second and third state.

98. The capacitor array circuit of claim 69 wherein the second capacitor is connected in series with the first capacitor between two of the nodes in the second state, the third capacitor is connected in series with the second capacitor between two of the nodes in the third state and the first capacitor is connected in series with the third capacitor between two of the nodes in the fourth state.

99. The capacitor array circuit of claim 98 wherein the first, second and third capacitors are connected in series between the input and third nodes in the first state, the first and second capacitors are connected in series between the output node and the third node in the second state, the second and third capacitors are connected in series between the output node and the third node in the third state and the third and first capacitors are connected in series between the output node an the third node in the fourth state.

100. The capacitor array circuit of claim 98 wherein the first, second and third capacitors are connected in series between the input and third nodes in the first state, the first and second capacitors are connected in series between the input node and the output node in the second state, the second and third capacitors are connected in series between the input node and the output node in the third state and the third and first capacitors are connected in series between the input node and the output node in the fourth state.

101. The capacitor array circuit of claim 98 wherein the first, second and third capacitors are connected in series between the output and third nodes in the first state, the first and second capacitors are connected in series between the input node and the output node in the second state, the second and third capacitors are connected in series between the input node and the output node in the third state and the third and first capacitors are connected in series between the input node an the output node in the fourth state.

102. A method of controlling a capacitor array circuit coupled to an input node, an output node and a third node, with the circuit including first and second capacitors, said method comprising:

switching the array circuit to a first state where the first and second capacitors are connected in series between two of the nodes;

switching the array circuit from the first state to a second state, different than the first state and where at least one of the first and second capacitors is connected between two of the input, output and third nodes;

switching the array circuit from the second state to a third state, different than the first and second states and where at least one of the first and second capacitors is connected between two of the input, output and third nodes, so that a voltage across each capacitor is a fixed proportion of a voltage at the input node and so that the array circuit has a fixed gain when the array circuit is in the first, second and third states and wherein in at least one of the first, second and third states, none of the first and second capacitors is connected between the input and output nodes.

103. The method of claim 102 wherein the second state, the first capacitor is connected between a first pair of the nodes and wherein in the third state, the second capacitor is connected between the first pair of the nodes.

104. The method of claim 103 wherein the first and second capacitors are connected in series between the third node and another one of the nodes in the first state and wherein first pair of the nodes in the second and third states are the input and output nodes.

105. The method of claim 102 wherein the capacitor array circuit further includes a third capacitor and wherein the switching the array circuit from the first state to the second state and the switching the array circuit from the second state to the third state results in the voltages across each of the capacitors is a fixed proportion of a voltage at the input node and wherein in at least one of the first, second and third states, none of the first, second and third capacitors is connected between the input and output nodes.

106. The method of claim 105 wherein the first, second and third capacitors are connected in series between two of the nodes in the first state.

107. The method of claim 105 further including switching the array circuit from the third state to a fourth state different from the first, second and third states.

108. The method of claim 107 wherein each of the second, third and fourth states, at least one of the first, second and third capacitors is connected between two of the nodes.

109. The method of claim 108 wherein in the first state one of the two nodes is the third node and in each of the second, third and fourth states, at least one of the first, second and third capacitors is connected between the input and output nodes.

110. A method of controlling a capacitor array circuit coupled to an input node an output node and a third node, with the circuit including first, second and third capacitors, said method comprising:

switching the array circuit to a first state where the first and second capacitors are connected in series between two of the nodes;

switching the array circuit from the first state to a second state, different than the first state where at least one of the capacitors is connected between two of the nodes;

switching the array circuit from the second state to a third state, different than the first and second states, where at least one of the capacitors is connected between two of the nodes; and

switching the array circuit from the third state to a fourth state, different from the first, second and third states, where at least one of the capacitors is connected between two of the nodes and wherein the array circuit has a fixed array gain in the first, second and third states and wherein in at least one of the first, second, third and fourth states, none of the first, second and third capacitors is connected between the input and output nodes.

111. The method of claim 110 wherein in the first state, the first and second capacitors are connected in series between the third node and another one of the nodes, wherein at least one of the capacitors is connected between the input and the output nodes in each of the second, third and fourth states.

112. The method of claim 111 wherein the first, second and third capacitors are connected in series in the first state.

113. The method of claim 112 wherein the first second and third capacitors are respectively connected between two of the nodes in the second, third and fourth states, respectively.

114. The method of claim 113 wherein the first and second capacitors are connected in series between a pair of the nodes in the second state, the second and third capacitors are connected in series between the pair of the nodes in the third state and the third and first capacitors are connected in series between the pair of the nodes in the fourth state.

115. A capacitor array circuit connected to an input node, an output node and a third node, said capacitor array circuit comprising:

first, second and third capacitors, with each capacitor having first and second terminals;

switching circuitry coupled to the first, second and third capacitors and to the input, output and third node;

control circuitry coupled to the switching circuitry and operative to sequentially switch the array circuit through at least three different states so that a voltage developed across each of the first, second and third capacitors is a fixed proportion of a voltage at the input node and wherein the array circuit has a fixed array gain in the first, second and third states, wherein each of the first, second and third capacitors is connected intermediate two of the input, output and third nodes in each of the first, second and third states and wherein in at least one of the first, second and third states, none of the first, second and third capacitors is connected between the input and output nodes.

116. The capacitor array circuit of claim 115 wherein the first, second and third capacitors are connected in series between two of the nodes in the first state.

117. The capacitor array circuit of claim 116 wherein the third capacitor is connected in parallel with the first capacitor between two of the nodes in the second state and the second capacitor is connected between two of the nodes in the third state.

118. The capacitor array circuit of claim 117 wherein one of the nodes in the first state is the third node, one of the nodes in the second state is the third node and one of the nodes in the third state is the third node.

119. The capacitor array circuit of claim 118 wherein one of the nodes in the first state is the input node and one of the nodes in the second state is the output node and one of the nodes in the third state is the output node.

120. The capacitor array circuit of claim 118 wherein one of the nodes in the first state is the output node and one of the nodes in the second state is the input node and one of the nodes in the third state is the input node.

121. The capacitor array circuit of claim 118 wherein the nodes in the first state are the input and output nodes, the nodes in the second and third states are the input and third node.

122. The capacitor array circuit of claim 121 wherein the first terminals of the first, second and third capacitors are facing the output node in the first state, the first terminals of the first and third capacitors are facing the input node in the second state and the first terminal of the second capacitor is facing input node in the third state.