System and method for highly phased power regulation

• US 6,563,294 B2
• Filed: 04/01/2002
• Issued: 05/13/2003
• Est. Priority Date: 10/10/2000
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Primarion Incorporated (Infineon Technologies AG)
• Inventors: Goodfellow, Ryan, Duffy, Thomas P., Susak, David
• Primary Examiner(s): NGUYEN, MATTHEW VAN
• Application Number:
  US10/112,738
• Publication Number:
  US 20020118001A1
• Time in Patent Office: 407 Days
• Field of Search: 323/265, 323/266, 323/268, 323/269, 323/271, 323/282, 323/283, 323/285
• US Class Current: 323/283
• CPC Class Codes: H02J 1/102 being switching converters H02J1/108, H02J1/12 take precedence
• CPC Class Codes: H02M 1/008 Plural converter units for generating at two or more independent and non-parallel outputs, e.g. systems with plural point of load switching regulators
• CPC Class Codes: H02M 3/157 with digital control
• CPC Class Codes: H02M 3/1584 with a plurality of power processing stages connected in parallel
• CPC Class Codes: H02M 7/493 the static converters being arranged for operation in parallel

Abstract

A highly phased power regulation (converter) system having an improved control feature is provided. A controller, such as a digital signal processor or microprocessor, receives digital information from a plurality of power conversion blocks and transmits control commands in response to the information. The controller is able to change the mode of operation of the system and/or re-phase the power blocks to accommodate a dynamic load requirement, occasions of high transient response or detection of a fault. In one embodiment, a microprocessor receives digital information and converted power from one or more power blocks. In this manner, the microprocessor is able to receive feedback on its own operation. The controller is also able to anticipate and predict conditions by analyzing precursor data. In this manner, the controller is able to modify the system as needed in anticipation of the forthcoming event.

Claims

1. A power regulation system coupled to an input source voltage (Vin) and an output voltage (Vout), said Vout electrically coupled to a load, the system comprising:

a plurality of power conversion blocks in a multi-phase configuration, each block electrically coupled to said Vin at a power IC and coupled to said Vout at an output inductance, said power IC including a command interface having read/write capabilities for storing data;

a controller in communication with and providing an instruction to said power conversion blocks, said controller having a plurality of adaptive algorithms configured to receive power conversion data from said blocks and to determine said instruction based on said power conversion data, said controller determining said multi-phase configuration and capable of re-phasing said blocks in response to said power conversion data; and

a digital bus providing a communication channel between said plurality of power conversion blocks and said controller.

2. The power regulation system of claim 1, wherein said controller comprises one of a digital signal processor (DSP) or a microprocessor.

3. The power regulation system of claim 1, further comprising a current feedback line between each of said power conversion blocks and said controller to facilitate current balancing.

4. The power regulation system of claim 1, wherein said command interface of said power IC further comprises a fault register.

5. The power regulation system of claim 4, wherein said controller periodically polls said fault register via said digital bus to determine if a fault within said power IC has occurred.

6. The power regulation system of claim 1, wherein each of said power ICs comprises an identification (ID) as assigned by said controller.

7. The power regulation system of claim 1, wherein said controller comprises a predictive control algorithm.

8. The power regulation system of claim 1, wherein said power conversion data comprises prediction control data and said controller provides said instruction in anticipation of a predicted condition.

9. The power regulation system of claim 1, wherein said power conversion data and said instruction comprise a mode of operation.

10. The power regulation system of claim 9, wherein said mode of operation includes one of pulse width modulation, constant ON time variable frequency, constant ON or OFF time and variable frequency, simultaneous phases ON, simultaneous phases OFF, active transient response high, active transient response low, continuous conduction or discontinuous conduction.

11. The power regulation system of claim 10, further comprising a multi-mode system wherein said controller provides a change of mode of operation instruction to said power block.

12. A method of controlling a multi-phased power regulation system, said method comprising the steps of:

receiving, at a controller, a plurality of digital information from each of a plurality of power conversion blocks in a multi-phase configuration, said information relating to an operation of said power conversion block;

analyzing said received information to include prediction of anticipated conditions;

transmitting a plurality of control information from said controller to each of said power conversion blocks in response to said analyzing step;

re-phasing said power conversion blocks in response to said analyzing step; and

changing to a different mode of operation of said power conversion blocks in response to said analyzing step.

13. The method of claim 12 further comprising the step of periodically polling a fault register of each of said power conversion blocks to receive fault information.

14. The method of claim 13 further comprising the steps of:

analyzing said fault information;

removing a faulty power conversion block from said multi-phase configuration; and

re-phasing the remaining power conversion blocks.

15. The method of claim 12 wherein said controller comprises a microprocessor and said receiving step occurs at said microprocessor.

16. The method of claim 12 further comprising the step of forming a synchronized current share line between said controller and each of said power conversion blocks.

17. The method of claim 12 further comprising the step of addressing each of said power conversion blocks.

18. The method of claim 17 further comprising the step of determining a number of available power conversion blocks in response to said addressing step.

19. The method of claim 18 further comprising the step of determining a relative phase relationship between a plurality of channels in response to said addressing step.

20. The method of claim 12 wherein said changing step comprises changing to one of pulse width modulation, constant ON time variable frequency, constant ON or OFF time and variable frequency, simultaneous phase ON, simultaneous phase OFF, active transient response high, active transient response low, continuous conduction, or discontinuous conduction.

21. The method of claim 12 wherein said changing step comprises changing to an active transient response mode and said controller instructs a plurality of FETs within said power conversion block to remain ON.

22. A multi operational mode power converter comprising:

a plurality of power ICs, each of said power ICs receiving a voltage input (Vin) and outputting a converted voltage (Vout);

a microprocessor in electrical communication with said plurality of power ICs, said microprocessor receiving said Vout from at least one of said power ICs and receiving a plurality of digital data from each of said power ICs, said microprocessor providing a control instruction to said power ICs in response to said received digital data, said control instruction comprising a mode of operation; and

a digital communication channel coupled to said microprocessor and said plurality of power ICs for transmission of said digital data and said control instruction.

23. The power converter of claim 22, wherein said digital communication channel comprises a digital backplane.

24. The power converter of claim 22, wherein said digital communication channel comprises an optical backplane.

25. The power converter of claim 22, further comprising a plurality of control algorithms stored on said microprocessor.

26. The power converter of claim 22, wherein said digital data comprises anticipatory operational information and said control instruction comprises a predictive control mode of operation.