Dynamic register with IDDQ testing capability

• US 6,563,333 B2
• Filed: 05/15/2002
• Issued: 05/13/2003
• Est. Priority Date: 11/13/1998
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Hatamian, Mehdi
• Primary Examiner(s): Cuneo, Kamand
• Assistant Examiner(s): Tang, Minh N.
• Application Number:
  US10/145,919
• Publication Number:
  US 20020163353A1
• Time in Patent Office: 363 Days
• Field of Search: 324/765, 324/768, 324/769, 324/158.1, 326/21, 326/93, 326/113, 326/119, 327/202, 327/203, 327/211, 327/396, 327/401, 365/189.12, 365/222, 365/239, 365/240
• US Class Current: 324/762.02
• CPC Class Codes: G01R 31/3004 Current or voltage test
• CPC Class Codes: G01R 31/3008 Quiescent current [IDDQ] test or leakage current test
• CPC Class Codes: G01R 31/3012 Built-In-Current test [BIC]
• CPC Class Codes: G01R 31/3016 Delay or race condition test, e.g. race hazard test
• CPC Class Codes: G01R 31/31715 Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
• CPC Class Codes: G01R 31/318502 Test of Combinational circuits
• CPC Class Codes: G01R 31/318552 Clock circuits details
• CPC Class Codes: G01R 31/318594 Timing aspects clock circuits G01R31/318552
• CPC Class Codes: H04B 3/23 using a replica of transmitted signal in the time domain, e.g. echo cancellers
• CPC Class Codes: H04B 3/32 Reducing cross-talk, e.g. by compensating
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 1/242 by comparing a transmitted test signal with a locally generated replica
• CPC Class Codes: H04L 2025/03363 Multilevel H04L2025/03369 takes precedence
• CPC Class Codes: H04L 2025/03369 Partial response
• CPC Class Codes: H04L 2025/03477 not time-recursive
• CPC Class Codes: H04L 2025/0349 as a feedback filter
• CPC Class Codes: H04L 2025/03496 as a prediction filter
• CPC Class Codes: H04L 2025/03503 as a combination of feedback and prediction filters
• CPC Class Codes: H04L 2025/03617 Time recursive algorithms H04L2025/03643 takes precedence
• CPC Class Codes: H04L 2025/03745 Timing of adaptation
• CPC Class Codes: H04L 25/03038 : with a non-recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03057 : with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03146 : with a recursive structure H04L25/03127 takes precedence
• CPC Class Codes: H04L 25/03267 : with decision feedback equalisers
• CPC Class Codes: H04L 25/067 : providing soft decisions, i.e. decisions together with an estimate of reliability H04L25/068 and H04L25/069 take precedence; sequence estimation techniques H04L25/03178
• CPC Class Codes: H04L 25/14 : Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 25/4917 : using multilevel codes
• CPC Class Codes: H04L 25/497 : by correlative coding, e.g. partial response coding or echo modulation coding transmitters and receivers for partial response systems transversal equalizers at the transmitter end H04L25/03343
• CPC Class Codes: H04L 7/0062 : detection of error based on data decision error, e.g. Mueller type detection
• CPC Class Codes: H04L 7/0334 : Processing of samples having at least three levels, e.g. soft decisions

Abstract

The present invention is a method and a system for controlling a voltage at a node in a circuit such that the node is prevented from having an unknown floating voltage during a steady state of a clock signal. The circuit includes a transmission gate which has input and output terminals, and operates in response to a clock signal. The node is located proximal to the output terminal of the transmission gate. The method includes the operations of driving the node with an input signal when the transmission gate is open during a first steady state of the clock signal and pulling the node to a fixed voltage when the transmission gate is closed during a second steady state of the clock signal.

Claims

1. A method for controlling a voltage at a node in a circuit including a transmission gate that has an input terminal and an output terminal, the node being coupled to the output terminal of the transmission gate, the method comprising the operations of:

(a) determining whether the transmission gate is open or closed;

(b) determining whether the circuit is under test; and

(c) if the transmission gate is closed and the circuit is under test, pulling the node to a fixed voltage.

2. The method of claim 1 further comprising the operation of:

(d) if the transmission gate is open, driving the node with an input signal.

3. The method of claim 1 wherein determining operation (b) comprises determining whether the circuit is under test based upon a value of a circuit test signal.

4. The method of claim 3 wherein the circuit is determined to be under test when the circuit test signal is of a predetermined value.

5. The method of claim 1 wherein a substantial amount of power supply current is prevented from dissipating in the circuit.

6. The method of claim 4 wherein the operations are facilitated by a control circuit, the control circuit including a logic gate and a transistor, the logic gate having an output and being responsive to the circuit test signal, the transistor having a gate terminal coupled to the output of the logic gate, the control circuit being coupled to the node via the transistor.

7. The method of claim 6 wherein the circuit test signal indicates whether the circuit is undergoing an IDDQ test.

8. The method of claim 6 wherein the logic gate is a NAND gate.

9. The method of claim 6 wherein the logic gate is an AND gate.

10. The method of claim 1 wherein the circuit includes an inverter disposed in series with the transmission gate, the node being located between the transmission gate and the inverter.

11. The method of claim 1 wherein the transmission gate is of CMOS type.

12. The method of claim 7 further comprising the operation of:

(d) if the transmission gate is open, driving the node with an input signal.

13. The method of claim 12 wherein driving operation (d) comprises turning off the transistor in the control circuit at substantially the same time as the transmission gate is opened, so that the control circuit does not affect the voltage at the node.

14. The method of claim 7 wherein pulling operation (c) comprises turning on the transistor in the control circuit at substantially the same time as the transmission gate is closed, so as to pull the voltage of the node to a fixed voltage via the transistor.

15. The method of claim 6 wherein the circuit is a dynamic register.

16. The method of claim 15 wherein the dynamic register is included in a gigabit transceiver chip.

17. A system for controlling a voltage at a node in a circuit including a transmission gate that has an input terminal and an output terminal, the node being connected to the output terminal of the transmission gate, the system comprising:

a control circuit coupled to the circuit at the node, the control circuit being adapted to pull the node to a fixed voltage if the transmission gate is closed and the circuit is under test.

18. The system of claim 17 further comprising:

an input signal adapted to drive the node if the transmission gate is open.

19. The system of claim 17 further comprising:

means for determining whether the circuit is under test.

20. The system of claim 19 wherein the means for determining whether the circuit is under test comprises a circuit test signal, wherein the circuit is determined to be under test when the circuit test signal is of a predetermined value.

21. The system of claim 17 wherein a substantial amount of power supply current is prevented from dissipating in the circuit.

22. The system of claim 20 wherein the control circuit includes a logic gate and a transistor, the logic gate having an output and being responsive to the circuit test signal, the transistor having a gate terminal coupled to the output of the logic gate, the control circuit being coupled to the node via the transistor.

23. The system of claim 22 wherein the circuit test signal indicates whether the circuit is undergoing an IDDQ test.

24. The system of claim 22 wherein the logic gate is a NAND gate.

25. The system of claim 22 wherein the logic gate is an AND gate.

26. The system of claim 17 wherein the circuit includes an inverter disposed in series with the transmission gate, the node being located between the transmission gate and the inverter.

27. The system of claim 17 wherein the transmission gate is of CMOS type.

28. The system of claim 23 further comprising:

an input signal adapted to chive the node if the transmission gate is open.

29. The system of claim 28 wherein the control circuit turns off the transistor in the control circuit at substantially the same time as the transmission gate is opened, so that the control circuit does not affect the voltage at the node.

30. The system of claim 23 wherein the control circuit turns on the transistor in the control circuit at substantially the same time as the transmission gate is closed, so as to pull the voltage of the node to a fixed voltage via the transistor.

31. The system of claim 22 wherein the circuit is a dynamic register.

32. The system of claim 31 wherein the dynamic register is included in a gigabit transceiver chip.