Flexible sample rate converter for multimedia digital-to-analog conversion in a wireless telephone
First Claim
1. A digital-to-analog converter, comprising:
- a dual frequency divider, for dividing a system clock signal by a divisor selected from a pair of adjacent integers, to produce a sampling clock;
a first sigma-delta modulator, for selecting the divisor for the dual frequency divider;
a second sigma-delta modulator, for selecting an oversampling multiple from a pair of adjacent integers;
a sampling latch, for sampling an input digital datastream synchronously with the sampling clock;
a digital filter, having an input receiving the sampled input digital datastream and an input receiving the selected oversampling multiple in the form of a digital word, for generating a reconstructed datastream corresponding to the input digital datastream; and
a digital-to-analog converter circuitry for producing an analog signal from the reconstructed datastream.
1 Assignment
0 Petitions
Accused Products
Abstract
A wireless telephone (40) is disclosed, in which audio input/output circuitry (44) includes a digital-to-analog conversion function (50) for producing an analog output signal (s(t)) based upon a digital baseband signal (S) from a digital signal processor (42). The digital-to-analog conversion function (50) includes first and second ΣΔ modulators (46, 48), each of which are controlled by a sampling clock generated by a dual frequency divider (47) controlled by the first ΣΔ modulator (46). A sampling latch (49) samples the digital baseband signal synchronously with the sampling clock. The second ΣΔ modulator (48) selects an oversampling multiple that is applied to a digit filter (52) along with the sampled signal from the sampling latch (49). The digital filter (52) reconstructs a digital signal from the sampled value and the oversampling multiple that is the equivalent of that reconstructed by the decimation of an over sampled signal. The reconstructed signal is converted to analog by a digital-to-analog converter (56). However, the digital filter (52) and DAC (56) can operate at a much lower frequency than in conventional circuits, thus providing excellent noise performance without requiring high frequency clocking.
65 Citations
23 Claims
-
1. A digital-to-analog converter, comprising:
-
a dual frequency divider, for dividing a system clock signal by a divisor selected from a pair of adjacent integers, to produce a sampling clock;
a first sigma-delta modulator, for selecting the divisor for the dual frequency divider;
a second sigma-delta modulator, for selecting an oversampling multiple from a pair of adjacent integers;
a sampling latch, for sampling an input digital datastream synchronously with the sampling clock;
a digital filter, having an input receiving the sampled input digital datastream and an input receiving the selected oversampling multiple in the form of a digital word, for generating a reconstructed datastream corresponding to the input digital datastream; and
a digital-to-analog converter circuitry for producing an analog signal from the reconstructed datastream. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
a third sigma-delta modulator, for producing a lower-resolution modulated signal from the reconstructed datastream; and
a digital-to-analog converter, for producing the analog signal form the lower-resolution modulated signal.
-
-
3. The converter of claim 1, further comprising:
-
a frequency divider, for producing a DAC clock having a frequency divided down from the frequency a system clock;
wherein the DAC clock is coupled to the digital filter and to the digital-to-analog converter circuitry.
-
-
4. The converter of claim 3, wherein the input digital datastream has a bandwidth;
wherein the sampling clock has an average frequency at approximately the sampling frequency of the input digital datastream.
-
5. The converter of claim 1, wherein the digital filter comprises:
-
circuitry for comparing a count value with a decimation ratio;
interpolation circuitry, for producing a weighted interpolation between a most recent value of the sampled input digital datastream and a previous value of the sampled input digital datastream;
a first multiplexer, for selecting either an interpolated value of the sampled input digital datastream from the interpolation circuitry or a selected value of the sampled input digital datastream responsive to the comparing circuitry, as an output value from the digital filter; and
circuitry for updating the count value responsive to the comparing circuitry.
-
-
6. The converter of claim 5, wherein the updating circuitry comprises:
-
a first adder for deriving a difference between the decimation value and the count value;
a second adder for adding the difference from the first adder to a current value of the oversampling multiple from the second sigma-delta modulator; and
a second multiplexer, for selecting the output of the first adder or the output of the second adder to produce an updated count value responsive to the comparing step.
-
-
7. The converter of claim 6, wherein the digital filter further comprises:
-
an output latch, clocked by the DAC clock, for storing the selected output of the first multiplexer; and
a counter latch, clocked by the DAC clock, for storing the selected output of of the second multiplexer.
-
-
8. The converter of claim 5, wherein the digital filter further comprises:
an output latch, clocked by the DAC clock, for storing the selected output of the first multiplexer.
-
9. The converter of claim 5, wherein the sampling latch comprises:
-
a first latch, clocked by the sampling clock, for storing the most recent value of the input digital datastream; and
a second latch, clocked by the sampling clock, having an input coupled to an output of the first latch, for storing the previous value of the input digital datastream.
-
-
10. The converter of claim 1, wherein the sampling latch comprises:
-
a first latch, clocked by the sampling clock, for storing a most recent value of the input digital datastream; and
a second latch, clocked by the sampling clock, having an input coupled to an output of the first latch, for storing a previous value of the input digital datastream.
-
-
11. The converter of claim 1, further comprising a digital signal processor for performing the digital filter.
-
12. A method of converting an input digital datastream, having a bandwidth, to an analog signal, comprising the steps of:
-
controlling a dual frequency divider to divide a system clock signal by a divisor selected from an adjacent pair of integers, to produce a sampling clock having an average frequency divided from the frequency of the system clock by a value between the pair of integers;
sampling the input digital datastream responsive to the sampling clock;
generating a sequence of digital words corresponding to oversampling multiples selected from an adjacent pair of integers;
reconstructing a digital datastream from the sampled input digital datastream and the sequence of oversampling multiples; and
converting the reconstructed digital datastream to an analog signal. - View Dependent Claims (13, 14, 15, 16)
performing sigma-delta modulation synchronously with the sampling clock to produce a sequence of control bits; and
applying the control bits to the dual frequency divider.
-
-
14. The method of claim 13, wherein the step of generating the sequence of digital words corresponding to oversampling multiples comprises:
-
performing sigma-delta modulation synchronously with the sampling clock to produce a sequence of increment bits; and
adding the increment bits to a base oversampling multiple to produce the digital words.
-
-
15. The method of claim 12, wherein the reconstructing step comprises:
-
deriving a weighted interpolation between a most recent value of the sampled input digital datastream and a previous value of the sampled input digital datastream;
comparing a count value with a decimation ratio;
selecting, for an output value, either the weighted interpolation or a selected value of the sampled input digital datastream responsive to the comparing step; and
updating the count value responsive to the comparing step.
-
-
16. The method of claim 15, wherein the updating step comprises:
-
deriving a difference between the decimation value and the count value;
adding the difference to a current value of the oversampling multiple; and
responsive to the comparing step, selecting the difference or the result of the adding step as an updated count value.
-
-
17. A wireless telephone, comprising:
-
an RF transceiver, for receiving and transmitting RF signals from and to a wireless network;
digital signal processing circuitry, coupled to the RF transceiver, for performing digital signal processing operations upon signals to be transmitted and received signals;
a speaker; and
audio input/output circuitry, coupled to the digital signal processing circuitry, for driving the speaker with an analog audio signal corresponding to digital baseband audio signals produced by the digital signal processing circuitry, the audio input/output circuitry including a digital-to-analog conversion function that comprises;
a dual frequency divider, for dividing a system clock signal by a divisor selected from a pair of adjacent integers, to produce a sampling clock;
a first sigma-delta modulator, for selecting the divisor for the dual frequency divider;
a second sigma-delta modulator, for selecting an oversampling multiple from a pair of adjacent integers;
a sampling latch, for sampling an input digital baseband datastream synchronously with the sampling clock;
a digital filter, having an input receiving the sampled input digital baseband datastream and an input receiving the selected oversampling multiple in the form of a digital word, for generating a reconstructed datastream corresponding to the input digital baseband datastream; and
digital-to-analog converter circuitry for producing an analog signal from the reconstructed datastream. - View Dependent Claims (18, 19, 20, 21, 22, 23)
a frequency divider, for producing a DAC clock having a frequency divided down from the frequency of a system clock;
wherein the DAC clock is coupled to the digital filter and to the digital-to-analog converter circuitry.
-
-
20. The telephone of claim 17, wherein the input digital datastream has a bandwidth;
wherein the sampling clock has an average frequency equal to the sampling frequency of the input digital datastream.
-
21. The telephone of claim 17, wherein the digital filter comprises:
-
circuitry for comparing a count value with a decimation ratio;
interpolation circuitry, for producing a weighted interpolation between a most recent value of the sampled input digital baseband datastream and a previous value of the sampled input digital baseband datastream;
a first multiplexer, for selecting either an interpolated value of the sampled input digital baseband datastream from the interpolation circuitry or a selected value of the sampled input digital baseband datastream responsive to the comparing circuitry, as an output value from the digital filter; and
circuitry for updating the count value responsive to the comparing circuitry.
-
-
22. The telephone of claim 21, wherein the updating circuitry comprises:
-
a first adder for deriving a difference between the decimation value and the count value;
a second adder for adding the difference from the first adder to a current value of the oversampling multiple from the second sigma-delta modulator; and
a second multiplexer, for selecting the output of the first adder or the output of the second adder to produce an updated count value responsive to the comparing step;
and wherein the digital filter further comprises;
an output latch, clocked by the DAC clock, for storing the selected output of the first multiplexer;
a counter latch, clocked by the DAC clock, for storing the selected output of the second multiplexer; and
an output latch, clocked by the DAC clock, for storing the selected output of the first multiplexer.
-
-
23. The telephone of claim 17, wherein the sampling latch comprises:
-
a first latch, clocked by the sampling clock, for storing the most recent value of the input digital baseband datastream; and
a second latch, clocked by the sampling clock, having an input coupled to an output of the first latch, for storing the previous value of the input digital baseband datastream.
-
Specification