Light sensor with increased dynamic range

• US 6,563,540 B2
• Filed: 02/26/1999
• Issued: 05/13/2003
• Est. Priority Date: 02/26/1999
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Nguyen, Dung C., Trevino, Roy T., Hirt, E. Ray
• Primary Examiner(s): Garber, Wendy R.
• Assistant Examiner(s): NGUYEN, LUONG TRUNG
• Application Number:
  US09/259,738
• Publication Number:
  US 20020012056A1
• Time in Patent Office: 1,537 Days
• Field of Search: 348/302, 348/308, 348/311, 257/222, 257/231, 257/291, 257/292
• US Class Current: 348/302
• CPC Class Codes: H04N 23/70 Circuitry for compensating brightness variation in the scene

Abstract

In an image capture system having a sensor with a first node and a second node, a method of capturing image data is disclosed. The first node is reset. The second node is reset. An image is collected on the first node. A first pixel value is then transferred from the first node to the second node after a first predetermined time period. The first pixel value and a second pixel value is then provided after a second predetermined time period. An arithmetic operation is performed on the first pixel value and the second pixel value. A system for performing the method is also disclosed.

Claims

1. In an image capture system having a sensor, the sensor having a plurality of pixel cells each having a first node and a second node and a third node and a fourth node, a method of capturing image data from a selected pixel cell, comprising:

performing two captures at the same time on the selected pixel cell with one capture having a longer integration time period than another, by

a) resetting the second node of the selected pixel cell;

b) resetting the first node of the selected pixel cell; and

then

c) collecting an image on the first node of the selected pixel cell; and

then

d) transferring a first pixel value from the first node to the second node after a first predetermined nonzero time period being the integration time period of one capture during which the image is collected on the first node but not the second node; and

then

e) reading a second pixel value from the first node via the third node of the selected pixel cell, and reading the first pixel value from the second node via the fourth node of the selected pixel cell, after a second predetermined nonzero time period that follows the first time period and during which the image is collected on the first node, a sum of the first and second time periods being the longer integration time period of another capture; and

f) performing an arithmetic operation on the first pixel value and the second pixel value to generate a result; and

g) providing the result as a value of the selected pixel cell, to the image capture system.

2. The method of claim 1 wherein performing an arithmetic operation on the first pixel value and the second pixel value includes determining a weighted average between the first pixel value and the second pixel value.

3. The method of claim 1, wherein providing the result to the image capture system includes performing an analog-to-digital conversion on the result.

4. The method of claim 1, wherein performing an arithmetic operation on the first pixel value and the second pixel value includes performing an analog-to-digital conversion on the first pixel value and the second pixel value before the arithmetic operation is performed.

5. The method of claim 1, wherein the first node and the second node are substantially segregated electronically other than when transferring the first pixel value.

19. The method of claim 3 wherein the first and second pixel values are read simultaneously at the end of the second time period.

6. In an image capture system having a sensor and a controller for controlling the sensor, the sensor including a pixel array having a plurality of pixel cells arranged in rows and columns, each pixel cell having a first node for collecting an image, a second node, a third node and a fourth node, a focal plane processor for processing a first pixel value and a second pixel value, a method of capturing image data from a selected pixel cell, comprising:

performing two captures at the same time on the selected pixel cell with one capture having a longer integration time period than another, by

a) the controller asserting a second reset signal to reset the second node to a predetermined value;

b) the controller asserting a first reset signal to reset the first node to a predetermined value; and

then

c) the pixel cell collecting an image on the first node represented by the first pixel value, and not on the second node; and

then

d) the controller asserting a first transfer signal to transfer the first pixel value from the first node to be stored at the second node after a first predetermined time period being the integration time period of one capture during which the image is collected on the first node; and

then

e) the controller asserting a first readout signal to read the second pixel value from the first node via the third node and to provide a second readout signal to read the first pixel value stored at the second node via the fourth node, after a second predetermined time period that follows the first time period and during which the image is collected on the first node, a sum of the first and second time periods being the longer integration time period of another capture; and

then

f) the focal plane processor performing an arithmetic operation on the first pixel value and the second pixel value to generate a result; and

then

g) the focal plane processor providing the result, as a value of the selected pixel, to the image capture system.

7. The method of claim 6 wherein the focal plane processor performing an arithmetic operation includes determining a weighted average between the first pixel value and the second pixel value.

8. The method of claim 6, wherein the focal plane processor providing the result to the image capture system includes the focal plane processor performing an analog-to-digital conversion on the result.

9. The method of claim 6 wherein the predetermined value is approximately 0 volts.

10. The method of claim 7, wherein the focal plane processor performing an arithmetic operation on the first pixel value and the second pixel value includes the focal plane processor performing an analog-to-digital conversion on the first pixel value and the second pixel value before the arithmetic operation is performed.

11. The method of claim 6, wherein the controller keeps the first node and the second node substantially segregated electronically other than when the first transfer signal is asserted.

20. The method of claim 6 wherein the first and second pixel values are read simultaneously at the end of the second time period.

12. An image capture system comprising:

a) a sensor for capturing image data having

i) a pixel array having a plurality of pixel cells arranged in rows and columns, each pixel cell having a first node for collecting image data, a second node, a third node, and a fourth node;

ii) a first data conductor, coupled to the third node for communicating a first pixel value from each of a group of pixel cells in one of a row and a column of the array;

iii) a second data conductor, coupled to the fourth node for communicating a second pixel value from each of the group of pixel cells;

iv) a focal plane processor coupled to the first data conductor and the second data conductor for receiving the first pixel value and the second pixel value, respectively, and responsive thereto performing an arithmetic operation on the first pixel value and the second pixel value to generate a result, the focal plane processor having an output for providing the result;

v) an interface circuit, coupled to the output of each focal plane processor, for interfacing the focal plane processor to a bus; and

b) a controller, coupled to the sensor, for controlling the sensor for managing the transfer of data from the pixel cell to the focal plane processor, for controlling the focal plane processor, for managing the transfer of data from the focal plane processor to the interface circuit, for controlling the interface circuit and for managing the transfer of data to the bus;

wherein the controller controls the sensor to generate a value representing the image detected by a selected pixel cell by performing two captures at the same time on the selected pixel cell with one capture having a longer integration time period than another to yield the first and second pixel values having different, nonzero integration times, the first and second pixel values being obtained by the first node of the selected pixel, the second pixel value being stored at the second node prior to being transferred to the fourth node.

13. The image capture system of claim 12 wherein the controller is a microcontroller.

14. The image capture system of claim 12 wherein the focal plane processor includes a weighted average circuit.

15. The image capture system of claim 12 wherein each pixel cell includes a first readout circuit for providing the first pixel value and a second readout circuit for providing the second pixel value.

16. The image capture system of claim 15 wherein the interface circuit includes a correlated double sampler.

17. The image capture system of claim 16 wherein the interface circuit further includes an amplifier coupled to the correlated double sampler for providing gain to the output of the correlated double sampler.

18. The image capture system of claim 17 wherein the interface circuit further includes an analog-to-digital converter coupled to the amplifier for converting the analog output of the amplifier to a digital value suitable for transmission on the bus.

21. The image capture system of claim 12 wherein the sensor has been implemented by a complimentary metal oxide semiconductor (CMOS) integrated circuit fabrication process.

22. The image capture system of claim 15 wherein in each pixel cell, the first and second readout circuits are to receive separate readout signals that control the transfer of data from the pixel cell to the focal plane processor.

23. The image capture system of claim 22 wherein each of the first and second readout circuits includes a source follower in series with a switch that is controlled by one of the separate readout signals.

24. The image capture system of claim 23 wherein each pixel cell has a photodiode that defines the first node and is coupled to provide a charge signal to an input of the source follower.

25. The image capture system of claim 22 wherein the first readout circuit is coupled between the third node and the first node, and the second readout circuit is coupled between the fourth node and the second node.

26. The image capture system of claim 22 wherein the sensor is part of a silicon eye that includes optics and that can communicate image data, captured by the sensor, over a computer peripheral bus with which the silicon eye can interface.

27. The image capture system of claim 26 wherein the silicon eye is attached to a display device and can receive sensor control parameters, including one that represents electronic shutter speed for the sensor, over the peripheral bus.

28. The image capture system of claim 26 wherein the silicon eye is part of a portable digital camera that includes a removable memory card to store the image data captured by the sensor.