System and method for transferring data between different types of memory using a common data bus

• US 6,563,739 B2
• Filed: 12/21/2000
• Issued: 05/13/2003
• Est. Priority Date: 12/22/1999
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: Nokia Mobile Phones UK Limited (Nokia Corporation)
• Inventors: Aho, Ari, Lipponen, Markku, Floman, Matti
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US09/740,802
• Publication Number:
  US 20010019509A1
• Time in Patent Office: 873 Days
• Field of Search: 365/185.08, 365/185.23, 365/233, 365/230.03, 365/185.11
• US Class Current: 365/185.23
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70

Abstract

A memory controller for controlling the transfer of data to and from a memory array, wherein the memory array includes a first type of memory and a second type of memory, the first type having a different signalling protocol from the second type of memory, wherein the memory controller comprises:

an address decoder having an input for receiving a memory access request, said memory access request including the address of the memory array to be accessed, and an output for outputting the address of the memory array to be accessed;

a first sub-controller for generating a plurality of memory interface signals for controlling the first type of memory, said first sub-controller being operated in response to addresses within a first range of addresses output by the address decoder; and

a second sub-controller for generating a plurality of memory interface signals for controlling the second type of memory, said second sub-controller being operated in response to addresses within a second, non-overlapping range of addresses output by the address decoder.

Claims

1. A system, which controls the transfer of data to and from a plurality of types of memory with each memory type using a different signalling protocol, the system comprising:

a controller;

at least one address bus coupling the controller to the plurality of types of memory; and

a single data bus, coupling the controller to a plurality of types of memory, which transmits the data between the controller and the types of memory; and

wherein

the controller controls transmitting of addressing signals on the at least one address bus to at least one of the plurality of types of memory to selectively transfer the data to and from storage locations in each of the types of memory.

2. A system according to claim 1 wherein:

one of the memory types is a burst mode memory.

3. A system according to claim 1 wherein:

one of the memory types is flash memory.

4. A system according to claim 1 wherein:

one of the memory types is ROM.

5. A system according to claim 1 comprising:

an additional type of memory.

6. A system in accordance with claim 5 wherein:

the additional type of memory is Synchronous Dynamic Random Access Memory.

7. A system according to claim 5 wherein:

parameters of the controller are configurable.

8. A system in accordance with claim 1 wherein:

parameters of the controller are configurable.

9. A system as claimed in claim 1 comprising:

an electronic telecommunications device.

10. A method of controlling the transfer of data in a system including a plurality of types of memory with each type of memory using a different signalling protocol, a controller which generates a plurality of memory control signals, a single data bus, coupling the controller to the types of memory, which transmits data between the controller and the types of memory and at least one address bus coupling the controller to the plurality of types of memory comprising:

transmitting the data on the single data bus between the controller and the types of memory; and

the controller controls transmitting of addressing signals on the at least one address bus to at least one of the plurality of types of memory to selectively transfer the data to and from storage locations in each of the types of memory.

11. A method in accordance with claim 10 wherein:

one of the address busses is combined with the data bus and addressing signals and the data are transmitted on the combined bus between the controller and the types of memory.

12. A method in accordance with claim 11 comprising:

configuring parameters of the memory.

13. A method in accordance with claim 10 comprising:

configuring parameters of the memory.

14. A system, which controls the transfer of data to and from a plurality of types of memory with each memory type using a different signalling protocol, the system comprising:

a controller;

a single data bus, coupling the controller to a plurality of types of memory, which transmits the data between the controller and the types of memory; and

a plurality of address busses coupling the controller to the types of memory; and

wherein

the plurality of address busses transmit addressing signals from the controller to the types of memory which address storage locations in the types of memory to selectively transfer the data to and from the storage locations in each of the types of memory.

15. A system in accordance with claim 14 wherein:

one of the address busses is combined with the data bus.

16. A system in accordance with claim 15 wherein;

the one of the address busses is coupled to a single type of memory.

17. A system in accordance with claim 16 wherein:

a number of address and data bits carried by the combined one address and data bus is identical.

18. A method of controlling the transfer of data in a system including a plurality of types of memory with each type of memory using a different signalling protocol, a controller which generates a plurality of memory control signals and a single data bus, coupling the controller to the types of memory, which transmits data between the controller and the types of memory and a plurality of address busses coupling the controller to the types of memory comprising:

transmitting the data on the single data bus between the controller and the types of memory; and

wherein

the plurality of address busses transmit addressing signals from the controller to the types of memory to selectively transfer the data to and from the storage locations in each of the types of memory.

19. A method in accordance with claim 18 comprising:

configuring parameters of the memory.