Memory device and method for dynamic bit inversion

• US 6,563,745 B1
• Filed: 12/14/2001
• Issued: 05/13/2003
• Est. Priority Date: 12/14/2001
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Ilkbahar, Alper
• Primary Examiner(s): Lam, David
• Application Number:
  US10/023,466
• Time in Patent Office: 515 Days
• Field of Search: 365/189.07, 365/189.02, 365/189.12, 365/236, 365/240, 365/230.08, 365/189.05
• US Class Current: 365/189.07
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

A memory device and method for storing bits in a memory array is provided. In one preferred embodiment, a memory device is provided comprising a plurality of memory cells that are in a first digital state and can be switched to a second digital state. A plurality of bits to be stored in the memory array are provided, and if the plurality of bits comprise more bits in the second digital state than in the first digital state, the plurality of bits are inverted before being stored in the memory array. In another preferred embodiment, a memory device is provided comprising a memory array and bit inversion circuitry. In yet another preferred embodiment, a plurality of bits are inverted before being stored in a memory array if the plurality of bits comprise more bits in a non-preferred digital state than in a preferred digital state.

Claims

1. A method for storing bits in a memory array, the method comprising:

(a) providing a plurality of bits to be stored in a memory array comprising a plurality of memory cells that are in a first digital state and that can be switched to a second digital state;

(b) determining whether the plurality of bits comprise more bits in the second digital state than in the first digital state; and

(c) if the plurality of bits comprise more bits in the second digital state than in the first digital state;

(c1) inverting the plurality of bits; and

(c2) storing the inverted plurality of bits in the memory array.

2. The invention of claim 1, wherein act (b) is performed by a memory device comprising the memory array.

3. The invention of claim 1, wherein the memory array is part of a memory device coupled with a host device, and wherein act (b) is performed by the host device.

4. The invention of claim 1, wherein act (c1) is performed by a memory device comprising the memory array.

5. The invention of claim 1, wherein the memory array is part of a memory device coupled with a host device, and wherein act (c1) is performed by the host device.

6. The invention of claim 1, further comprising:

(d) if the plurality of bits comprise more bits in the first digital state than in the second digital state, storing the plurality of bits in the memory array without inverting the plurality of bits.

7. The invention of claim 1, further comprising:

(d) if the plurality of bits comprise an equal number of bits in the first and second digital.states, storing the plurality of bits in the memory array without inverting the plurality of bits.

8. The invention of claim 1, further comprising,

(d) if the plurality of bits comprise an equal number of bits in the first and second digital states:

(d1) inverting the plurality of bits; and

(d2) storing the inverted plurality of bits in the memory array.

9. The invention of claim 1, wherein less programming time is spent storing a bit in the first digital state than in storing a bit in the second digital state.

10. The invention of claim 1, wherein (c2) comprises programming memory cells associated with bits in the second digital state and skipping memory cells associated with bits in the first digital state.

11. The invention of claim 1, further comprising:

(c3) storing data in the memory array indicating that the plurality of bits were stored in an inverted state.

12. The invention of claim 1, further comprising:

(c3) reading the inverted plurality of bits from the memory array; and

(c4) inverting the inverted plurality of bits read from the memory array.

13. The invention of claim 1, wherein the plurality of bits comprise a page.

14. The invention of claim 1, wherein the plurality of bits comprise two oct-bytes.

15. The invention of claim 1, wherein the plurality of bits comprise a minimum amount of data that can be written to the memory array.

16. The invention of claim 1, wherein the plurality of memory cells comprise write-once memory cells, wherein the first digital state comprises an initial un-programmed state of the write-once memory cells, and wherein the second digital state comprises a programmed state of the write-once memory cells.

17. The invention of claim 1, wherein the memory array comprises a three-dimensional memory array.

18. The invention of claim 1, wherein the plurality of memory cells are made from a semiconductor material.

19. A memory device comprising:

a memory array comprising a plurality of memory cells that are in a first digital state and that can be switched to a second digital state; and

bit inversion circuitry coupled with the memory array, the bit inversion circuitry being operative to determine whether a plurality of bits comprise more bits in the second digital state than in the first digital state and being further operative to invert the plurality of bits before they are stored in the memory array if the plurality of bits comprise more bits in the second digital state than in the first digital state.

20. The invention of claim 19, wherein the bit inversion circuitry comprises an inverter, a multiplexor, a counter, and a decision stack.

21. The invention of claim 19, wherein the bit inversion circuitry is further operative to invert the stored inverted plurality of bits when they are read from the memory array.

22. The invention of claim 19, further comprising a page register coupled with the bit inversion circuitry.

23. The invention of claim 22, further comprising an oct-byte register coupled with the page register.

24. The invention of claim 19, wherein the plurality of memory cells comprise write-once memory cells, wherein the first digital state comprises an initial un-programmed state of the write-once memory cells, and wherein the second digital state comprises a programmed state of the write-once memory cells.

25. The invention of claim 19, wherein the memory array comprises a three-dimensional memory array.

26. The invention of claim 19, wherein the plurality of memory cells are made from a semiconductor material.

27. A memory device comprising:

a memory array comprising a plurality of memory cells that are in a first digital state and that can be switched to a second digital state; and

means for determining whether a plurality of bits comprise more bits in the second digital state than in the first digital state and for inverting the plurality of bits before they are stored in the memory array if the plurality of bits comprise more bits in the second digital state than in the first digital state.

28. The invention of claim 27, wherein the means comprises an inverter, a multiplexor, a counter, and a decision stack.

29. The invention of claim 27, further comprising a page register coupled with the means for determining and inverting.

30. The invention of claim 29, further comprising an oct-byte register coupled with the page register.

31. A method for storing bits in a memory array, the method comprising:

(a) providing a plurality of bits to be stored in a memory array comprising a plurality of memory cells that are in a first digital state and that can be switched to a second digital state;

(b) determining whether the plurality of bits comprise more bits in a non-preferred digital state than in a preferred digital state; and

(c) if the plurality of bits comprise more bits in the non-preferred digital state than in the preferred digital state;

(c1) inverting the plurality of bits; and

(c2) storing the inverted plurality of bits in the memory array.

32. The invention of claim 31, wherein the preferred digital state comprises the first digital state.

33. The invention of claim 31, wherein the preferred digital state comprises the second digital state.

34. The invention of claim 31, wherein the preferred digital state improves the performance of the memory device.

35. The invention of claim 31, wherein the preferred digital state improves write bandwidth of the memory device.

36. The invention of claim 31, wherein the preferred digital state improves power consumption of the memory device.

37. The invention of claim 31, wherein the preferred digital state improves reliability of the memory device.

38. The invention of claim 31, wherein the preferred digital state improves leakage.

39. The invention of claim 31, wherein act (b) is performed by a memory device comprising the memory array.

40. The invention of claim 31, wherein the memory-array is part of a memory device coupled with a host device, and wherein act (b) is performed by the host device.

41. The invention of claim 31, wherein act (c1) is performed by a memory device comprising the memory array.

42. The invention of claim 31, wherein the memory array is part of a memory device coupled with a host device, and wherein act (c1) is performed by the host device.

43. The invention of claim 31, further comprising:

(d) if the plurality of bits comprise more bits in the preferred digital state than in the non-preferred digital state, storing the plurality of bits in the memory array without inverting the plurality of bits.

44. The invention of claim 31, further comprising:

(d) if the plurality of bits comprise an equal number of bits in the preferred digital state and the non-preferred digital state, storing the plurality of bits in the memory array without inverting the plurality of bits.

45. The invention of claim 31, further comprising:

(d) if the plurality of bits comprise an equal number of bits in the preferred digital state and the non-preferred digital state;

(d1) inverting the plurality of bits; and

(d2) storing the inverted plurality of bits in the memory array.

46. The invention of claim 31, further comprising:

(c3) storing data in the memory array indicating that the plurality of bits were stored in an inverted state.

47. The invention of claim 31, further comprising:

(c3) reading the inverted plurality of bits from the memory array; and

(c4) inverting the inverted plurality of bits read from the memory array.

48. The invention of claim 31, wherein the plurality of memory cells comprise write-once memory cells, wherein the first digital state comprises an initial un-programmed state of the write-once memory cells, and wherein the:

second digital state comprises a programmed state of the write-once memory cells.

49. The invention of claim 31, wherein the memory array comprises a three-dimensional memory array.

50. The invention of claim 31, wherein the plurality of memory cells are made from a semiconductor material.