Automatic gain control for slotted mode operation

• US 6,563,891 B1
• Filed: 11/05/1999
• Issued: 05/13/2003
• Est. Priority Date: 11/24/1998
• Status: Expired due to Term

• Current Assignee: Telefonaktiebolaget LM Ericsson
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Gustafsson, Kjell Berthold, Eriksson, Håkan Bengt, Dent, Paul Wilkinson
• Primary Examiner(s): Le, Amanda T.
• Application Number:
  US09/434,444
• Time in Patent Office: 1,285 Days
• Field of Search: 375/345, 455/234.1, 455/234.2, 455/240.1, 455/241.1, 455/244.1, 455/245.1, 455/249.1, 455/251.1, 329/350
• US Class Current: 375/345
• CPC Class Codes: H03G 1/0023 in emitter-coupled or cascode amplifiers H03G1/0029 takes precedence
• CPC Class Codes: H03G 3/3078 Circuits generating control signals for digitally modulated signals

Abstract

A receiver having a digital automatic gain control (AGC) circuit is disclosed for use in a cellular communication system, including a Hierarchical Cellular System. The receiver includes a controller which switches between gain control values depending on system operational mode. In this way, the AGC can be optimized for different types of receive processing operations, e.g., traffic reception and measurement of other channels.

Claims

1. A receiver, comprising:

an amplifier for amplifying a received signal, the amplifier having gain control by an automatic gain control (AGC) system and producing an amplified signal;

a state memory for storing a plurality of states, each state comprising a set of parameters stored in mutual association, the parameters including at least a receiver operating mode, a channel frequency, an AGC gain setting value, and an AGC time constant;

an analog-to-digital converter for converting said amplified signal into a stream of digital values; and

a processor configured to;

receive said stream of digital values; and

selectively retrieve a state from said state memory, thereby controlling a gain of said gain controlled amplifier using a first of said sets of parameters associated with a first receiver operating mode or alternatively using a second of said sets of parameters associated with a second receiver operating mode or at least a third of said sets of parameters associated with a third receiver operating mode.

2. The receiver of claim 1, wherein said first mode is a traffic mode for receiving said signal on a traffic frequency channel assigned to said receiver, said second mode is a measurement mode for measuring signals on other frequency channels, and said third mode is a sleep mode in which said receiver is at least partly powered down to conserve power.

3. The receiver of claim 1, wherein said first mode is a sleep mode wherein said receiver is operating at a first power level said second mode is an operative mode wherein said receiver is operating at a second power level greater than said first power level.

4. The receiver of claim 1, wherein said processor determines a mean signal level output by said analog-to-digital converter using a low-pass filter.

5. The receiver of claim 4, wherein said low-pass filter is a first order filter and wherein said first set of parameter values includes a first filter time constant value and said a second set of parameter values includes a second filter time constant value different than said first filter time constant value.

6. The receiver of claim 5, wherein said first mode is a traffic mode for receiving said signal on a traffic channel assigned to said receiver and said second mode is a measurement mode for measuring signals on other channels, and wherein said first filter time constant value provides for a smaller filter bandwidth than said second filter time constant value.

7. The receiver of claim 4, wherein said low pass filter is a second or higher order filter.

8. The receiver of claim 4, wherein said processor further comprises:

a control loop for comparing said mean signal level with a target means signal level and controlling said gain based on said comparison, said control loop including at least one variable parameter which is set using a value selected from said first and second set of parameter values depending upon whether said receiver is operating in said first or second mode of operation, respectively.

9. The receiver of claim 8, wherein said at least one variable parameter is a scaling factor which determines a speed at which automatic gain control is performed.

10. The receiver of claim 8, wherein said control loop includes as said at least one variable parameter a value of a settable accumulator.

11. The receiver of claim 1, further comprising a memory device for storing said first and second sets of parameter values.

12. The receiver of claim 11, wherein each of said first and second sets of parameter values include:

a first value associated with a filter time constant, a second value associated with a filter'"'"'s accumulator value, a third value associated with a scaling factor, and a fourth value associated with an integrator'"'"'s accumulator value.

13. The receiver of claim 11, wherein said processor is also operable to adjust said gain based on at least one additional mode of operation and wherein said memory device includes a set of parameter values for each said at least one additional mode of operation.

14. The receiver of claim 1, further comprising:

a timer for determining an elapsed time since one of said first and second sets of parameter values were used by said processor;

wherein said processor uses a default set of parameter values if said elapsed time is greater than a threshold and wherein said processor predicts a set of parameter values based on a stored set of parameter values and said elapsed time if said elapsed time is less than said threshold.

15. The receiver of claim 1, wherein said first mode is an idle mode from which the receiver has awoken to receive a control channel signal on a first channel and said second mode is an idle mode from which the receiver has awoken to measure the signal strength on a second channel.

16. A receiver, comprising:

a gain controlled amplifier having a feedback control loop for amplifying a received signal;

a mode selector for selecting one of a plurality of modes;

an analog-to-digital converter for converting said amplified signal into a stream of digital values; and

a processor configured to;

receive said stream of digital values; and

selectively control a gain of said gain controlled amplifier using a first set of parameter values when said receiver is operating in a first of said plurality of modes, a second set of parameter values when said receiver is operating in a second of said plurality of modes, and at least a third set of parameter values when said receiver is operating in a third of said plurality of modes;

wherein said processor determines a mean signal level output by said analog-to-digital converter using a low-pass filter, said low-pass filter is a first order filter, said first set of parameter values includes a first filter time constant value and said second set of parameter values includes a second filter time constant value different from said first filter time constant value, and said first order filter includes a settable accumulator, which accumulator can be set by said processor using a value selected from said first, second and third set of parameter values depending upon whether said receiver is operating in said first, second, or third mode of operation, respectively.

17. A method for controlling a digital automatic gain control (AGC) circuit in a receiver, the method comprising the steps of:

operating said receiver in a first mode to receive signals on a traffic frequency channel assigned thereto;

switching to a second mode;

operating said receiver in said second mode to measure signal strengths associated with frequency channels other than said traffic frequency channel;

controlling a gain associated with an amplifier in said receiver by using a set of parameter values associated with said second mode of operation to process received signals after said receiver is switched to operate in said second mode, which set of parameter values is different for said first mode than said second mode; and

switching to a third mode of operation of said receiver.

18. The method of claim 17, wherein said step of switching further comprises the steps of:

operating said receiver in a sleep mode to periodically awaken and receive signals in an assigned paging channel time slot;

switching from said sleep mode to an active mode wherein said receiver uses more power; and

operating said receiver in said active mode to receive traffic signals.

19. The method of claim 17, further comprising the steps of:

A/D converting an output of said amplifier to generate a digital signal; and

determining a mean signal level of said digital signal using a low-pass filter.

20. The method of claim 19, wherein said low-pass filter is a first order filter and wherein said set of parameter values for said first mode includes a first filter time constant value and said of parameter values for said second mode includes a second filter time constant value different than said first filter time constant value.

21. The method of claim 20, wherein said first mode is a traffic mode for receiving said signal on a traffic channel assigned to said receiver and said second mode is a measurement mode for measuring signals on other channels, and wherein said first filter time constant value provides for a smaller filter bandwidth than said second filter time constant value.

22. The method of claim 20, wherein said first order filter includes a settable accumulator, which accumulator can be set by said processor using a value selected from said first and second set of parameter values depending upon whether said receiver is operating in said first or second mode of operation, respectively.

23. The method of claim 19, wherein said low pass filter is a second or higher order filter.

24. The method of claim 19, further comprising the steps of:

comparing said mean signal level with a target means signal level; and

controlling said gain based on said comparison, said control loop including at least one variable parameter which is set using a value selected from a first and second set of parameter values depending upon whether said receiver is operating in said first or second mode of operation, respectively.

25. The method of claim 24, wherein said at least one variable parameter is a scaling factor which determines a speed at which automatic gain control is performed.

26. The method of claim 24, wherein said at least one variable parameter a value of a settable accumnulator.

27. The method of claim 17, further comprising the step of:

storing said first said second, and a third sets of parameter values associated with said first, second, and third modes, respectively, wherein the parameter values include a receiver operating mode, a channel frequency, a gain control setting value, and a gain control time constant.

28. The method or claim 27, wherein each of said first and second sets of parameter values include:

a first value associated with a filter time constant, a second value associated with a filter'"'"'s accumulator value, a third value associated with a scaling factor, and a fourth value associated with an integrator'"'"'s accumulator value.

29. The method of claim 17, further comprising the step of:

determining an elapsed time since one of said first and second sets of parameter values were used by said processor;

wherein said processor uses a default set of parameter values if said elapsed time is greater than a threshold and wherein said processor predicts a set of parameter values based on a stored set of parameter values and said elapsed time if said elapsed time is less than said threshold.