Fieldbus message queuing method and apparatus

• US 6,564,268 B1
• Filed: 03/17/1999
• Issued: 05/13/2003
• Est. Priority Date: 03/17/1999
• Status: Expired due to Term

• Current Assignee: Rosemount Incorporated (Emerson Electric Company)
• Original Assignee: Rosemount Incorporated (Emerson Electric Company)
• Inventors: Davis, Bruce B., Kammann, Paul D.
• Primary Examiner(s): Gaffin, Jeffrey
• Assistant Examiner(s): Perveen, Rehana
• Application Number:
  US09/271,182
• Time in Patent Office: 1,518 Days
• Field of Search: 379/229, 700/83, 700/7, 375/368, 710/11, 710/33, 710/69
• US Class Current: 710/11
• CPC Class Codes: G05B 19/0423 Input/output
• CPC Class Codes: G05B 19/4185 characterised by the network communication
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

A method and apparatus are provided to allow at least portions of two fieldbus messages to be stored in a fieldbus device. The fieldbus device includes a media access unit, a fieldbus communication controller, and a controller. The media access unit is coupleable to a fieldbus loop to receive fieldbus signals and provide a digital bitstream related to the fieldbus signals. The fieldbus communication controller assembles data segments relating to at least portions of two fieldbus messages from the bitstream and stores the segments in a receive FIFO memory. The controller is adapted: to read the segments from the receive FIFO memory and act upon fieldbus messages.

Claims

1. A fieldbus device, comprising:

a media access unit, adapted to couple to a fieldbus loop and receive signals representative of fieldbus messages, and having a serial output interface;

a fieldbus communication controller having a serial input interface coupled to the serial output interface of the media access unit, and having a data output;

a controller having a data input interface coupled to the data output interface of the fieldbus communication controller; and

wherein the fieldbus communication controller includes a receive first-in-first-out (FIFO) memory and is adapted to simultaneously store at least portions of two fieldbus messages.

2. The fieldbus device of claim 1, wherein the data input interface of the controller is a parallel interface.

3. The fieldbus device of claim 1, wherein the controller is a direct memory access controller.

4. The fieldbus device of claim 1, wherein the fieldbus communication controller is an application specific integrated circuit.

5. The fieldbus device of claim 1, wherein the controller is a microprocessor.

6. The fieldbus device of claim 1, wherein the fieldbus communication controller includes a first pointer adapted to indicate an address of one of the at least portions of two fieldbus messages and a second pointer adapted to indicate a starting address of another of the at least two portions of fieldbus messages.

7. The fieldbus device of claim 1, and further comprising a sensor coupled to the controller and coupleable to a process, the sensor adapted to provide a sensor output to the controller based upon a process variable.

8. The fieldbus device of claim 1, and further comprising an actuator coupled to the controller and adapted to couple to a process to affect the process.

9. The fieldbus device of claim 1, wherein the serial output interface of the media access unit is adapted to provide data at a first rate of transmission, the data output of the fieldbus communication controller is adapted to provide data at a second rate of transmission which is faster than the first rate of transmission.

10. The fieldbus device of claim 9, wherein the first rate of transmission is less than about 1 megabit/second.

11. The fieldbus device of claim 10, wherein the first rate of transmission is about 31,250 bits/second.

12. The fieldbus device of claim 1 and further comprising a power supply coupleable to the fieldbus loop adapted to power the fieldbus device with power received from the fieldbus loop.

13. The fieldbus device of claim 1, wherein the fieldbus.loop comprises a two-wire loop.

14. The fieldbus device of claim 1, wherein the fieldbus loop comprises more than two conductors.

15. An application specific integrated circuit for storing at least portions of first and second fieldbus messages, the circuit comprising:

a serial input interface adapted to receive serial fieldbus data at a first transmission rate;

a data output adapted to provide fieldbus data at a second rate of transmission which is faster than the first rate of transmission;

a receive first-in-first-out (FIFO) memory coupled to the serial input interface and the data output and adapted to store a plurality of fieldbus data segments;

a first pointer adapted to indicate a segment location corresponding to a current receive first-in-first-out read location;

a second pointer adapted to indicate a segment location corresponding to a current receive first-in-first-out write location; and

a third pointer adapted to indicate a segment location corresponding to a first segment of a portion of the second fieldbus message.

16. The circuit of claim 15, and further comprising a counter adapted to maintain a count of a total number of fieldbus data segments stored in the receive first-in-first-out.

17. The circuit of claim 16 and further comprising:

a first flag adapted to indicate whether the receive first-in-first-out (FIFO) memory is empty;

a second flag adapted to indicate whether the receive first-in-first-out (FIFO) memory is full; and

a third flag adapted to indicate whether the circuit has received a fieldbus message.

18. The circuit of claim 17, and further comprising a fourth flag adapted to indicate whether an end segment of the first fieldbus message has been read from the receive first-in-first-out (FIFO) memory.

19. The circuit of claim 18, and further comprising an error flag adapted to indicate whether the second fieldbus message had been completely received before the first fieldbus message was read from the receive first-in-first-out (FIFO) memory.

20. The circuit of claim 19, and further comprising a status flag adapted to indicate whether the end segment of the first fieldbus message had been read from the receive first-in-first-out (FIFO) memory and whether the second fieldbus message was already in the receive first-in-first-out (FIFO) memory.

21. A method of receiving at least portions of multiple fieldbus messages, comprising:

serially receiving data representative of a first fieldbus message and at least a portion of a second fieldbus message;

assembling data representative of the first fieldbus message into at least one first-message segment;

storing the at least one first-message segment into a receive first-in-first-out (FIFO) memory;

assembling data representative of the at least a portion of the second fieldbus message into at least one second-message segment; and

storing the at least one second-message segment into the receive first-in-first-out (FIFO) memory while the at least one first-message segment is stored in the receive first-infirst-out (FIFO) memory.

22. The method of claim 21, and further comprising maintaining a count of a number of the at least one first-message segments stored in the receive first-in-first-out (FIFO) memory.

23. The method of claim 21, wherein the at least one first message segment comprises a plurality of segments.

24. The method of claim 21, and further comprising maintaining a pointer indicating a first segment of the at least one second message segment.

25. The method of claim 21, and further comprising maintaining a count of a total number of segments stored in the receive first-in-first-out (FIFO) memory.

26. A fieldbus computer program on computer readable media comprising:

receive first-in-first-out storage instructions for receiving at least portions of two fieldbus messages and storing the at least portions in a receive first-in-first-out (FIFO) memory;

pointer instructions for storing information related to an end segment location if the at least one fieldbus message segment is an end segment;

counting instructions that maintain a count of a total number of message segments stored in the receive first-in-first-out (FIFO) memory; and

reading instructions that iteratively read segments from incremental locations of the receive first-in-first-out (FIFO) memory based upon the number of segments stored in the receive first-in-first-out (FIFO) memory and the pointer information.

27. A fieldbus-device comprising:

means for receiving serial data corresponding to at least portions of two fieldbus messages from a fieldbus loop;

means for providing and storing data segments based upon the serial data; and

means for reading the data segments.