Method and apparatus for automatically transferring I/O blocks between a host system and a host adapter

• US 6,564,271 B2
• Filed: 06/09/1999
• Issued: 05/13/2003
• Est. Priority Date: 06/09/1999
• Status: Expired due to Term

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: QLogic Corporation (Marvell Technology Group Limited)
• Inventors: Konda, Dharma R., Micalizzi, Charles Jr., Sippy, Chandru M.
• Primary Examiner(s): Gaffin, Jeffrey
• Assistant Examiner(s): Nguyen, Tanh Q
• Application Number:
  US09/328,738
• Publication Number:
  US 20030056032A1
• Time in Patent Office: 1,434 Days
• Field of Search: 710/1, 710/3, 710/5, 710/7, 710/20, 710/22, 710/33, 710/39, 710/46, 710/48, 710/52, 710/53, 710/56, 710/57, 710/62, 710/72, 710/74, 710/260, 710/263, 711/1, 711/100, 711/147, 711/150
• US Class Current: 710/39
• CPC Class Codes: G06F 13/126 and has means for transferring I/O instructions and statuses between control unit and main processor

Abstract

An input/output (I/O) host adapter in an I/O system processes I/O requests from a host system to a plurality of I/O devices. The host adapter includes a circuit to automatically transfer I/O requests from host memory to adapter memory. The host adapter also includes a circuit to automatically transfer I/O responses from adapter memory to host memory.

Claims

1. A method for automatically loading I/O command blocks from a host system into an I/O command block buffer in a local memory of a host adapter, the command block buffer being used to store I/O command blocks to be processed by a processor on the host adapter, the method comprising:

monitoring a request queue to determine when an I/O command block is in said request queue;

determining a place in said request queue where said I/O command block resides;

determining if space is available to store the I/O command block at the I/O command block buffer in the local memory of the host adapter;

determining if space is available to store an address that will indicate where the I/O command block will be placed after being loaded into the I/O command block buffer;

retrieving a buffer address identified from an address list of free buffer locations;

transferring said I/O command block from said place in said request queue to a buffer location addressed by said buffer address; and

writing said buffer address to an address list of filled buffer locations.

2. The method of claim 1, wherein the monitoring of said request queue comprises using at least one register on the host adapter to exchange information between the host system and the host adapter.

3. The method of claim 1, wherein the transfer of said I/O command block from said place in said request queue to said buffer location involves a direct memory access (DMA) transfer operation.

4. The method of claim 1, wherein the host adapter is a Fibre Channel host adapter.

5. The method of claim 1, wherein the host system and the host adapter are coupled together by a peripheral component interconnect (PCI) bus.

6. A circuit for accelerating the processing of I/O commands from a host system to a host adapter, said circuit comprising:

a host adapter RAM;

a monitoring unit to monitor a request queue in host memory, wherein said monitoring unit generates a signal upon detection of at least one I/O command in said request queue;

a retrieval unit to transfer said at least one I/O command from its location in said request queue to a buffer location in said host adapter RAM responsive to said signal after determining if space is available for the I/O command and space is available to write an address of the location where the I/O command will be stored after transfer, wherein a buffer address of said buffer location is read from an address list of free buffer locations in said host adapter RAM, and wherein said buffer address is written to an address list of filled buffer locations in said host adapter RAM; and

a processor to process said I/O command in said buffer location, wherein said processor retrieves said buffer address from said address list of filled buffer locations, and wherein said processor writes said buffer address to said address list of free buffer locations after processing said I/O commands.

7. The circuit of claim 6, wherein the monitoring unit comprises at least one register on the host adapter used to exchange information between the host system and the host adapter.

8. The circuit of claim 6, wherein the retrieval unit transfers said new I/O command from said request queue to a buffer location in said host adapter RAM by a direct memory access (DMA) operation.

9. The circuit of claim 6, wherein the host adapter is a Fibre Channel host adapter.

10. The circuit of claim 6, wherein the host system and the host adapter are coupled by a peripheral component interface (PCI) bus.

11. The circuit of claim 6, wherein the monitoring unit and the retrieval unit are integrated into a single processor which executes instructions from the host adapter RAM.