Synchronous memory device having automatic precharge

• US 6,564,281 B2
• Filed: 10/01/2001
• Issued: 05/13/2003
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US09/969,489
• Publication Number:
  US 20020046314A1
• Time in Patent Office: 589 Days
• Field of Search: 365/194, 365/233, 365/189.02, 710/305
• US Class Current: 710/305
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/066 : Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 : Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 : Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 : Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A synchronous memory device including an array of memory cells. The memory device includes a plurality of sense amplifiers, coupled to the array of memory cells, to sense data. The memory device further includes input receiver circuitry to sample an operation code synchronously with respect to a transition of an external clock signal. The operation code including precharge information and, in response to the precharge information, the plurality of sense amplifiers are automatically precharged after the data is sensed.

Claims

1. A synchronous memory device including an array of memory cells, wherein the memory device comprises:

a plurality of sense amplifiers, coupled to the array of memory cells, to sense data; and

input receiver circuitry to sample an operation code synchronously with respect to a transition of an external clock signal, the operation code including precharge information, wherein, in response to the precharge information, the plurality of sense amplifiers are automatically precharged after the data is sensed.

2. The memory device of claim 1 further including output driver circuitry to output first and second portions of the data in response to the operation code specifying a read operation.

3. The memory device of claim 2 wherein:

the output driver circuitry outputs the first portion of the data synchronously with respect to a rising edge transition of the external clock signal; and

the output driver circuitry outputs a second portion of the data synchronously with respect to a falling edge transition of the external clock signal.

4. The memory device of claim 3 further including delay locked loop circuitry, coupled to the output driver circuitry, to generate an internal clock signal using the external clock signal, wherein the output driver circuitry outputs the first and second portions of the data in response to the internal clock signal.

5. The memory device of claim 2 further including a plurality of pads, wherein both the input receiver circuitry and the output driver circuitry are coupled to a common set of pads of the plurality of pads.

6. The memory device of claim 1 wherein the input receiver circuitry further includes a first input receiver to sample a first bit of the operation code synchronously with respect to the transition of the external clock signal, wherein the precharge information is encoded in the first bit of the operation code.

7. The memory device of claim 6 wherein the first input receiver further samples address information synchronously with respect to another transition of the external clock signal.

8. The memory device of claim 6 wherein the input receiver circuitry further includes a second input receiver to sample a second bit of the operation code synchronously with respect to the transition of the external clock signal, wherein the second bit of the operation code specifies a read operation, wherein a portion of the data is output from the memory device in response to the second bit of the operation code specifying the read operation.

9. The memory device of claim 8 wherein the input receiver circuitry further includes a third input receiver to sample address information synchronously with respect to a transition of the external clock signal.

10. The memory device of claim 1 wherein the operation code includes a plurality of bits, and wherein the plurality of bits encode information which specifies that the plurality of sense amplifiers sense the data from the array of memory cells.

11. The memory device of claim 1 further including:

row decoder circuitry, coupled to the array of memory cells, to identify, in response to a row address, a row of the array of memory cells to be sensed by the plurality of sense amplifiers.

12. The memory device of claim 11 further including column decoder circuitry, coupled to the array of memory cells, to identify, in response to a column address, a portion of the data.

13. The memory device of claim 12 wherein the input receiver circuitry includes a plurality of input receivers to sample:

the row address, synchronously with respect to the external clock signal; and

the column address, synchronously with respect to the external clock signal.

14. The memory device of claim 1 wherein the input receiver circuitry includes a plurality of input receivers to sample, in response to the operation code specifying a write operation, data to be stored in the array of memory cells.

15. The memory device of claim 14 wherein the operation code and a portion of the data to be stored in the array of memory cells are sampled using a common set of input receivers of the plurality of input receivers.

16. A synchronous memory device including an array of memory cells,

wherein the memory device comprises:

a clock receiver to receive an external clock signal;

a plurality of sense amplifiers, coupled to the array of memory cells, to sense data, wherein, in response to a first operation code bit specifying a read operation, first and second portions of the data are output from the memory device;

a first input receiver to sample the first operation code bit in response to a first transition of the external clock signal;

a second input receiver to sample a second operation code bit in response to the first transition of the external clock signal, wherein the second operation code bit indicates that precharging the plurality of sense amplifiers occur automatically after the data has been sensed; and

a plurality of output drivers to output the data, wherein;

the first portion of the data is output in response to a rising edge transition of the external clock signal; and

the second portion of the data is output in response to a falling edge transition of the external clock signal.

17. The memory device of claim 16 wherein the second input receiver further samples an address bit synchronously with respect to a second transition of the external clock signal.

18. The memory device of claim 16 wherein the plurality of output drivers output the first and second portions of the data onto an external bus, the external bus including a plurality of external signal lines.

19. The memory device of claim 18 wherein the first operation code bit is sampled from a first signal line of the plurality of external signal lines, and the second operation code bit is sampled from a second signal line of the plurality of external signal lines.

20. The memory device of claim 18 wherein the plurality of external signal lines is used to carry control and address information in a multiplexed format.

21. The memory device of claim 16 wherein:

in a first state, the second operation code bit indicates that precharging the plurality of sense amplifiers occur automatically after the data has been sensed; and

in a second state, the second operation code bit indicates that contents of the plurality of sense amplifiers be retained after the data has been sensed.

22. The memory device of claim 16 wherein:

in a first state, the first operation code bit specifies the read operation; and

in a second state, the first operation code bit specifies a write operation, wherein, in response to the first operation code bit specifying the write operation, data is input by the memory device.

23. The memory device of claim 16 further including a delay locked loop, coupled to the clock receiver, to generate an internal clock signal using the external clock signal, wherein the plurality of output drivers output the first and second portions of the data in response to the internal clock signal.

24. The memory device of claim 16 further including a programmable register to store a value which is representative of a number of clock cycles of the external clock signal to transpire before the memory device outputs the first portion of the data in response to the first operation code bit specifying the read operation.

25. The memory device of claim 16 further including a plurality of additional input receivers to sample block size information in response to a second transition of the external clock signal, wherein the block size information represents an amount of the data to be output in response to the first operation code bit specifying the read operation.

26. The memory device of claim 16 further including:

row decoder circuitry, coupled to the array of memory cells, to identify a row of the array of memory cells to be sensed by the plurality of sense amplifiers; and

column decoder circuitry, coupled to the array of memory cells, to identify locations of the first and second portions of the data.

27. A method of operation of a synchronous memory device, wherein the memory device includes an array of memory cells, wherein the method of operation of the memory device comprises:

sampling an operation code in response to a first transition of an external clock signal, wherein the operation code specifies a read operation and includes precharge information;

sensing data in a plurality of sense amplifiers, wherein the data is to be output in response to the operation code specifying the read operation;

automatically precharging the plurality of sense amplifiers in response to the precharge information, wherein the plurality of sense amplifiers is automatically precharged after the data is sensed;

outputting a first portion of the data synchronously with respect to a rising edge transition of the external clock signal; and

outputting a second portion of the data synchronously with respect to a falling edge transition of the external clock signal.

28. The method of claim 27 further including sampling address information synchronously with respect to the external clock signal.

29. The method of claim 28 wherein the operation code and the address information are included in a request packet.

30. The method of claim 28 wherein the operation code and the address information are sampled from an external bus, wherein the external bus includes a plurality of signal lines to carry the address information and the operation code in a multiplexed format.

31. The method of claim 30 wherein the first and second portions of the data are output onto the plurality of signal lines.

32. The method of claim 27 further including:

selecting a row of memory cell locations in accordance with a first address portion; and

sensing data, from the selected row of memory cell locations, in a row of sense amplifiers, wherein the plurality of sense amplifiers is included in the row of sense amplifiers.

33. The memory device of claim 32 further including selecting the plurality of sense amplifiers in accordance with a second address portion.

34. The method of claim 33 further including:

sampling the first address portion synchronously with respect to a transition of the external clock signal; and

sampling the second address portion synchronously with respect to another transition of the external clock signal.

35. The method of claim 27 further including sampling block size information in response to a second transition of the external clock signal, wherein the block size information represents an amount of the data sensed in the plurality of sense amplifiers to be output by the memory device in response to the operation code specifying the read operation.

36. A method of controlling a synchronous memory device, wherein the memory device includes a plurality of sense amplifiers coupled to an array of memory cells, wherein the method of controlling the memory device comprises:

issuing a first operation code to the memory device, wherein the first operation code indicates that the memory device;

output data read from the array of memory cells; and

precharge sense amplifiers used in reading the data from the array of memory cells, wherein the sense amplifiers are precharged automatically after the data is read from the array of memory cells; and

receiving the data from the memory device, the memory device outputting the data read from the array of memory cells in response to the first operation code.

37. The method of claim 36 wherein the first operation code is included in a request packet.

38. The method of claim 36 wherein the first operation code further includes a first bit wherein:

a first state of the first bit indicates that the memory device precharge the sense amplifiers used in reading the data from the array of memory cells; and

a second state of the first bit specifies that the memory device retain the data in the sense amplifiers used in reading the data from the array of memory cells.

39. The method of claim 38 wherein the first operation code includes a second bit wherein:

a first state of the second bit indicates that the memory device is to output the data read from the array of memory cells; and

a second state of the second bit indicates that the memory device is to input data, wherein the input data is to be written to the array of memory cells.

40. The method of claim 36 further including issuing a second operation code to the memory device, wherein the second operation code instructs the memory device to:

input data to be written to the array of memory cells;

write the input data to the array of memory cells using sense amplifiers of the plurality of sense amplifiers; and

precharge the sense amplifiers used in writing the input data to the array of memory cells, wherein the plurality of sense amplifiers are precharged automatically after the input data is written to the array of memory cells.

41. The method of claim 40 further including issuing a third operation code to the memory device, wherein the third operation code instructs the memory device to:

output data read from the array of memory cells; and

after reading the data from the array of memory cells, retain the data in sense amplifiers used to read the data from the array of memory cells.

42. The method of claim 36 further including providing block size information to the memory device wherein the block size information defines an amount of data read from the array of memory cells to be output from the memory device in response to the first operation code.

43. The method of claim 36 further including:

providing a value to the memory device, wherein the value is representative of a number of clock cycles of an external clock signal to transpire before the memory device outputs the data in response to the first operation code; and

issuing a second operation code to the memory device, wherein the second operation code initiates storage of the value, in a register internal to the memory device.

44. The method of claim 36 wherein the first operation code further includes a plurality of bits, wherein the plurality of bits encode information which instruct the memory device to read the data from the array of memory cells using the sense amplifiers.

45. The method of claim 36 further including issuing address information to the memory device, wherein the address information is issued synchronously with respect to the external clock signal.

46. The method of claim 45 wherein the address information and the first operation code are issued to the memory device via an external bus.