Synchronous interface for a nonvolatile memory

• US 6,564,285 B1
• Filed: 06/14/2000
• Issued: 05/13/2003
• Est. Priority Date: 06/03/1994
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Mills, Duane R., McCormick, Bruce, Pashley, Richard D., Sambandan, Sachidanandan, Dipert, Brian Lyn
• Primary Examiner(s): NGUYEN, THAN VINH
• Application Number:
  US09/595,327
• Time in Patent Office: 1,063 Days
• Field of Search: 711/100-106, 711/200-206, 711/167-169
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A flash memory chip that can be switched into four different read modes is described. In asynchronous flash mode, the flash memory is read as a standard flash memory. In synchronous flash mode, a clock signal is provided to the flash chip and a series of addresses belonging to a data burst are specified, one address per clock period. The data stored at the specified addresses are output sequentially during subsequent clock periods. In asynchronous DRAM mode, the flash memory emulates DRAM. In synchronous DRAM mode the flash memory emulates synchronous DRAM.

Claims

1. A method comprising:

a.) specifying a plurality of addresses corresponding to a data burst by receiving a plurality of multiplexed addresses and control signals including a first strobe signal and a second strobe signal, latching a first portion of a selected multiplexed address; and

latching a second portion of the selected multiplexed address, wherein the first and second portions form a demultiplexed address;

b.) reading data from a flash memory in accordance with the addresses;

c.) providing the data in synchronization with a clock signal; and

d.) repeating steps a) through c) in a burst read mode such that data stored at the plurality of addresses is provided sequentially during subsequent clock cycles.

2. The method of claim 1 wherein the first strobe signal is a row address signal, wherein latching a first portion of a selected multiplexed address is performed in response to the row address strobe signal.

3. The method of claim 1 wherein the second strobe signal is a column address signal, wherein latching a second portion of the selected multiplexed address is performed in response to the column address strobe signal.

4. The method of claim 1 further comprising the step of:

e) providing a tristated output if the control signals indicate a refresh cycle.

5. The method of claim 4 wherein a sequence of the first and second strobe signals is indicative of the refresh cycle.

6. The method of claim 1 further comprising the step of:

e) providing a tristated output memory if the control signals indicate a precharge cycle.

7. A method comprising:

a.) specifying a beginning address of a plurality of addresses corresponding to a data burst by receiving a plurality of multiplexed addresses and control signals including a first strobe signal and a second strobe signal, latching a first portion of a selected multiplexed start address; and

latching a second portion of the selected multiplexed start address, wherein the first and second portions form a demultiplexed address;

b.) reading data from a flash memory in accordance with the addresses;

c.) providing the data in synchronization with a clock signal;

d.) generating a burst read address as the beginning address; and

e.) repeating steps b) through d) in a burst read mode such that data stored at the plurality of addresses is provided sequentially, starting from the beginning address, during subsequent clock cycles.

8. The method of claim 7 wherein the first strobe signal is a row address signal, wherein latching a first portion of a selected multiplexed start address is performed in response to the row address strobe signal.

9. The method of claim 7 wherein the second strobe signal is a column address signal, wherein latching a second portion of the selected multiplexed start address is performed in response to the column address strobe signal.

10. The method of claim 7 further comprising the step of:

f.) providing a tristated output if the control signals indicate a refresh cycle.

11. The method of claim 7 wherein a sequence of the first and second strobe signals is indicative of the refresh cycle.

12. The method of claim 7 further comprising the step of:

f.) providing a tristated output memory if the control signals indicate a precharge cycle.

13. An apparatus comprising:

a plurality of flash memory banks, wherein consecutive addresses are interlace among the plurality of flash memory banks;

interlace control logic generating bank latch enable signals in accordance with received multiplexed address signals, asynchronous control signals, and synchronous control signals including a clock signal;

a plurality of bank latches to provide addresses to the plurality of banks in accordance with the bank latch enable signals; and

a mode register, wherein the interlace control logic provides synchronous access to the plurality of memory banks in accordance with the multiplexed address signals and synchronous control signals to provide synchronous burst read data on consecutive cycles of the clock signal if the mode register is storing a first value.

14. The apparatus of claim 13 formed within an integrated circuit.

15. The apparatus of claim 13 wherein the mode register is implemented with content addressable memory.

16. The apparatus of claim 13 wherein the first value is indicative of a synchronous dynamic random access memory (DRAM) mode of operation.

17. The apparatus of claim 13 wherein an output of the nonvolatile memory apparatus is tristated if the asynchronous control signals indicate a refresh cycle.

18. The apparatus of claim 13 wherein an output of the nonvolatile memory apparatus is tristated if the asynchronous control signals indicate a precharge cycle.