Wakeup circuit for computer system that enables codec controller to generate system interrupt in response to detection of a wake event by a codec

• US 6,564,330 B1
• Filed: 12/23/1999
• Issued: 05/13/2003
• Est. Priority Date: 12/23/1999
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Vadivelu, Karthi R., Poisner, David I., Martinez, Alberto J.
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): WANG, ALBERT C
• Application Number:
  US09/472,096
• Time in Patent Office: 1,237 Days
• Field of Search: 713/300, 713/323
• US Class Current: 713/322
• CPC Class Codes: G06F 1/24 Resetting means

Abstract

A wake up circuit for a computer system with a codec controller. The circuit provides a wakeup signal to the computer system when a codec detects an event that requires the system to become active. This signal is provided whether the communications link between the codecs and their controller is active or inactive. When the link is inactive, as indicated by the absence of a bit clock, a data signal on any of the codec input lines triggers the controller to send a power activation signal to the system and to initiate an activation of the codec link. If the link is already active, the general purpose input status change bit is transmitted to the controller, which writes it into a register that is used to trigger a power activation signal to the system. An enable input permits the wakeup signal to be enabled or disabled under program control. The wakeup signal can be used to trigger a system management interrupt or other interrupt suitable for initiating a system resume function.

Claims

1. A wakeup circuit, comprising:

a data circuit with a first data input to receive a first data input signal from a first codec;

a clock status circuit with a first clock status input to receive a clock status signal and a second clock status input coupled to an output of the data circuit;

a device status circuit with a first device status input to receive a device status signal and a second device status input coupled to an output of the clock status circuit; and

a wakeup status circuit with a first wakeup status input coupled to an output of the device status circuit to receive a wakeup status signal, and a wakeup status output to assert a wakeup signal if said device status signal is asserted and to assert said wakeup status signal if said clock status input signal is not asserted and said first data input signal is asserted.

2. The circuit of claim 1, wherein the wakeup status circuit further includes:

a second wakeup status input to receive a wakeup enable signal;

wherein said wakeup signal is asserted only if said wakeup enable signal is asserted and said wakeup status signal is asserted.

3. The circuit of claim 1, wherein the clock status signal indicates if a codec bit clock is active.

4. The circuit of claim 1, wherein the codec is one of an audio codec, a modem codec, and an audio/modem codec.

5. The circuit of claim 1, wherein the data circuit further includes a second data input to receive a second data input signal from a second codec, wherein said wakeup status signal is asserted if said clock status input signal is not asserted and at least one of said first and second data input signals is asserted.

6. The circuit of claim 5, wherein the first codec is an audio codec and the second codec is a modem codec.

7. A wakeup system for a computer, comprising:

a computer system;

a codec controller coupled to the computer system;

a first codec coupled to the codec controller through a codec link;

a status register coupled to the codec controller;

a wakeup circuit coupled to the status register and the codec link, said wakeup circuit including;

a data circuit with a first data input to receive a first data input signal from a first codec;

a clock status circuit with a first clock status input to receive a clock status signal and a second clock status input coupled to an output of the data circuit;

a device status circuit with a first device status input to receive a device status signal and a second device status input coupled to an output of the clock status circuit; and

a wakeup status circuit with a first wakeup status input coupled to an output of the device status circuit to receive a wakeup status signal, and a wakeup status output to assert a wakeup signal if said device status signal is asserted and to assert said wakeup status signal if said clock status input signal is not asserted and said first data input signal is asserted.

8. The circuit of claim 7, wherein the wakeup status circuit further includes:

a second wakeup status input to receive a wakeup enable signal;

wherein said wakeup signal is asserted only if said wakeup enable signal is asserted and said wakeup status signal is asserted.

9. The circuit of claim 7, wherein the clock status signal indicates if a codec bit clock in said codec link is active.

10. The circuit of claim 7, wherein the first codec is one of an audio codec, a modern codec, and an audio/modem codec.

11. The circuit of claim 7, further comprising a second data input for receiving a second data input signal from a second codec, wherein said wakeup status signal is asserted if said clock status input signal is not asserted and one of said first and second data input signals is asserted.

12. The circuit of claim 11, wherein the first codec is an audio codec and the second codec is a modem codec.

13. A method of waking a computer system, comprising:

detecting a wake event by a codec;

transmitting a status bit in a data transmission from the codec to a codec controller;

receiving the data transmission by the codec controller;

writing the status bit into a register;

generating a wakeup signal if the status bit in the register has a predetermined state;

generating a system interrupt; and

waking up the computer system.

14. The method of claim 13, wherein transmitting includes transmitting the status bit in a predefined bit of a predefined slot of a data frame.

15. The method of claim 14, the predefined slot is slot 12 and the predefined bit is bit 0.

16. The method of claim 13, wherein detecting a wake event includes detecting at least one of:

a modem ring indication;

a minimum analog amplitude indication; and

an analog waveform match indication.