Method of designing a layout of an LSI chip, and a computer product

• US 6,564,362 B2
• Filed: 02/22/2001
• Issued: 05/13/2003
• Est. Priority Date: 07/04/2000
• Status: Expired due to Term

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Osaki, Seiko, Abe, Koji
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): Lin, Sun James
• Application Number:
  US09/789,490
• Publication Number:
  US 20020004929A1
• Time in Patent Office: 810 Days
• Field of Search: 716/1-14
• US Class Current: 716/122
• CPC Class Codes: G01R 31/318538 Topological or mechanical aspects
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits
• CPC Class Codes: H01L 27/11898 Input and output buffer/driver structures

Abstract

In a method of designing a layout of an LSI chip, which LSI chip has boundary scan registers, after arranging I/O cells and before arranging an internal logic circuit and the like, I/O connection boundary scan registers are preferentially arranged in empty regions of the I/O cells. Output I/O control boundary scan registers are arranged at intermediate points between the I/O connection boundary scan registers, respectively, or a chip side closer to the intermediate points. Thereafter, before arranging cells constituting other circuits and creating a wiring pattern, buffer cells are inserted into nets of test signals to the boundary scan register led to a test control circuit.

Claims

1. A method of designing a layout of an LSI chip having boundary scan registers, the method comprising:

arranging I/O cells;

arranging I/O connection boundary scan registers to be connected to the I/O cells, in empty regions near connection target I/O cells among a group of the arranged I/O cells and along a scan chain that represents an order of scanning;

arranging output I/O control boundary scan registers adjacent to an edge of the LSI chip and along the scan chain, the output I/O control boundary scan registers to be connected to the I/O connection boundary scan registers, based on arrangement positions of a plurality of connection target I/O connection boundary scan registers among a group of the arranged I/O connection boundary scan registers;

making a fan-out adjustment to the arranged I/O connection boundary scan registers and output I/O control boundary scan registers;

arranging cells constituting other circuits in empty regions; and

creating a wiring pattern.

2. The method of designing a layout of an LSI chip according to claim 1, wherein

the output I/O control boundary scan registers are arranged at intermediate points between a plurality of connection target I/O connection boundary scan registers along the chain, respectively.

3. The method of designing a layout of an LSI chip according to claim 1, wherein

if a plurality of I/O connection boundary scan registers to which the output I/O control boundary scan registers are connected, are arranged along a pair of adjacent chip sides, the output I/O control boundary scan registers are arranged toward the chip side closer to intermediate points between the plurality of connection target I/O connection boundary scan registers out of the pair of chip sides.

4. The method of designing a layout of an LSI chip according to claim 1, wherein

the fan-out adjustment is made by calculating a tentative wiring length between the boundary scan registers arranged adjacent each other based on Manhattan lengths of the boundary scan registers, calculating an estimated wiring capacity based on the tentative wiring length, and inserting buffer cells into test signal nets based on the estimated wiring capacity, so that loads of input terminals of the boundary scan registers driven by the buffer cells, fall within a range of driving capabilities of output terminals of the buffer cells.

5. The method of designing a layout of an LSI chip according to claim 4, wherein

a correction coefficient for correcting a difference between the tentative wiring length and an actual wiring length is obtained in advance, and the driving capabilities of the output terminals of the buffer cells are corrected using the correction coefficient.

6. The method of designing a layout of an LSI chip according to claim 4, wherein

each of the buffer cells is arranged near the boundary scan register closest to a test control circuit among one or a plurality of boundary scan registers driven by the buffer cells.

7. A computer readable medium for storing instructions, which when executed on a computer, causes the computer to perform design layout of an LSI chip to execute:

arranging I/O cells;

arranging I/O connection boundary scan registers to be connected to the I/O cells, in empty regions near the connection target I/O cells among a group of the arranged I/O cells and along a scan chain that represents an order of scanning;

arranging output I/O control boundary scan registers adjacent to an edge of the LSI chip and along the scan chain, the output I/O control boundary scan registers to be connected to the I/O connection boundary scan registers, based on arrangement positions of a plurality of corresponding connection target I/O connection boundary scan registers among a group of the arranged I/O connection boundary scan registers;

making a fan-out adjustment to the arranged I/O connection boundary scan registers and output I/O control boundary scan registers;

arranging cells constituting other circuits in empty regions; and

creating a wiring pattern.

8. A computer readable recording medium according to claim 7, wherein

the computer program allows the computer to make the fan-out adjustment by calculating a tentative wiring length between the boundary scan registers arranged adjacent each other based on Manhattan lengths of the boundary scan registers, calculating an estimated wiring capacity based on the tentative wiring length, and inserting buffer cells into test signal nets based on the estimated wiring capacity so that loads of input terminals of the boundary scan registers driven by the buffer cells fall within a range of driving capabilities of output terminals of the buffer cells.

9. A method of designing a layout of an LSI chip, comprising:

arranging I/O cells;

arranging I/O connection boundary scan registers to be connected to the I/O cells, in empty regions near selected ones of the arranged I/O cells and along a scan chain that represents an order of scanning;

arranging output I/O control boundary scan registers adjacent to an edge of the LSI chip and along the scan chain, the output I/O control boundary scan registers to be connected to the I/O connection boundary scan registers;

making a fan-out adjustment to the arranged I/O connection boundary scan registers and output I/O control boundary scan registers;

arranging cells constituting additional circuits in empty regions; and

creating the wiring pattern.

10. A method as set forth in claim 9, further comprising arranging the output I/O control boundary scan registers toward a chip side closer to intermediate points between selected ones of the I/O connection boundary scan registers, if a plurality of the I/O connection boundary scan registers to which the output I/O control boundary scan registers are connected, are arranged along a pair of adjacent chip sides.