Process to define N/PMOS poly patterns

• US 6,566,184 B1
• Filed: 02/21/2002
• Issued: 05/20/2003
• Est. Priority Date: 02/21/2002
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wei, Zin-Chein, Lee, Chih-Hsiung, Huang, Chuan-Chieh
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US10/082,015
• Time in Patent Office: 453 Days
• Field of Search: 438/199, 438/231, 438/232, 438/279, 438/283, 438/527, 438/532
• US Class Current: 438/232
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures

Abstract

A method of fabricating doped polysilicon structures comprising the following steps. A substrate is provided and an undoped polysilicon layer is formed over the substrate. The undoped polysilicon layer is patterned to form at least one undoped polysilicon structure within an N area and at least one undoped polysilicon structure within a P area. The at least one undoped polysilicon structure within the N area is masked, leaving exposed an upper portion of the other at least one undoped polysilicon structure within the P area. The exposed at least one undoped polysilicon structure within the P area is doped to form a P-doped polysilicon structure. An upper portion of the masked at least one undoped polysilicon structure within the N area is unmasked and exposed, and the P-doped polysilicon structure is masked. The exposed at least one undoped polysilicon structure within the N area is doped to form an N-doped polysilicon structure to complete fabrication of the doped polysilicon structures.

Claims

1. A method of fabricating doped polysilicon structures, comprising the steps of:

providing a substrate;

forming an undoped polysilicon layer over the substrate;

patterning the undoped polysilicon layer to form at least one undoped polysilicon structure within an N area and at least one undoped polysilicon structure within a P area;

masking the;

substrate; and

at least one undoped polysilicon structure within the N area leaving exposed an upper portion of the other at least one undoped polysilicon structure within the P area;

doping the exposed at least one undoped polysilicon structure within the P area to form a P-doped polysilicon structure;

unmasking and exposing an upper portion of the masked at least one undoped polysilicon structure within the N area and masking the;

substrate; and

the P-doped polysilicon structure; and

doping the exposed at least one undoped polysilicon structure within the N area to form an N-doped polysilicon structure to complete fabrication of the doped polysilicon structures.

2. The method of claim 1, wherein the at least one N-doped polysilicon structure is formed before the at least one P-doped polysilicon structure.

3. The method of claim 1, wherein the polysilicon structures are gates.

4. The method of claim 1, wherein the substrate is a silicon substrate.

5. The method of claim 1, wherein the undoped polysilicon layer has a thickness of from about 1000 to 2500 Å

.

6. The method of claim 1, wherein the undoped polysilicon layer has a thickness of from about 1000 to 1500 Å

.

7. The method of claim 1, wherein the undoped polysilicon layer is patterned using an overlying patterned mask layer.

8. The method of claim 1, wherein the undoped polysilicon layer is patterned using an overlying patterned mask layer;

the overlying patterned mask layer being comprised of a material selected from the group consisting of photoresist, TEOS oxide, SiON and PEOX.

9. The method of claim 1, wherein the undoped polysilicon layer is patterned using an overlying patterned mask layer;

the overlying patterned mask layer being comprised of photoresist.

10. A method of fabricating doped polysilicon structures, comprising the steps of:

providing a substrate;

forming an undoped polysilicon layer over the substrate;

patterning the undoped polysilicon layer to form at least one undoped polysilicon structure within an N area and at least one undoped polysilicon structure within a P area;

forming a first photoresist layer over the substrate, covering and masking the N and P area polysilicon structures;

light exposing only the first photoresist layer within the P area;

whereby the P area light exposed first photoresist layer is removed at a greater rate than the N area non-light exposed first photoresist layer during dry development;

dry developing the partially exposed first photoresist layer to unmask only an upper portion of the P area polysilicon structure;

doping the unmasked P area polysilicon structure to form a P-doped polysilicon structure;

removing the dry developed first photoresist layer;

forming a second photoresist layer over the substrate, covering and masking the N area polysilicon structure and the P-doped polysilicon structure;

light exposing only the second photoresist layer within the N area;

whereby the N area light exposed second photoresist layer is removed at a greater rate than the P area non-light exposed second photoresist layer during dry development;

dry developing the partially exposed second photoresist layer to unmask only an upper portion of the N area polysilicon structure; and

doping the unmasked N area polysilicon structure to form a N-doped polysilicon structure to complete fabrication of the doped polysilicon structures.

11. The method of claim 10, wherein the polysilicon structures are gates.

12. The method of claim 10, wherein the N-doped polysilicon structure is formed before the P-doped polysilicon structure.

13. The method of claim 10, wherein the substrate is a silicon substrate.

14. The method of claim 10, wherein the undoped polysilicon layer has a thickness of from about 1000 to 2500 Å

.

15. The method of claim 10, wherein the undoped polysilicon layer has a thickness of from about 1000 to 1500 Å

.

16. The method of claim 10, wherein the first and second partially exposed photoresist layers are developed using a dry developer tool.

17. The method of claim 10, wherein the first and second partially exposed photoresist layers are developed using an O₂ plasma.

18. The method of claim 10, including the steps of:

removing the dry developed second photoresist layer after forming the N-doped polysilicon structure; and

further processing the structure.

19. The method of claim 10, wherein the undoped polysilicon layer is patterned using an overlying patterned mask layer.

20. The method of claim 10, wherein the undoped polysilicon layer is patterned using an overlying patterned mask layer;

the overlying patterned mask layer being comprised of a material selected from the group consisting of photoresist, TEOS oxide, SiON and PEOX.

21. The method of claim 10, wherein the undoped polysilicon layer is patterned using an overlying patterned mask layer;

the overlying patterned mask layer being comprised of photoresist.

22. A method of fabricating doped polysilicon structures, comprising the steps of:

providing a substrate;

forming an undoped polysilicon layer over the substrate;

patterning the undoped polysilicon layer to form at least one undoped polysilicon structure within an N area and at least one undoped polysilicon structure within a P area;

forming a first photoresist layer over the substrate, covering and masking the N and P area polysilicon structures;

etching back the first photoresist layer to expose only the upper portions of the N and P area polysilicon structures;

forming a first masking layer over the N area polysilicon structure and the etched back first photoresist layer only within the N area;

doping the unmasked P area polysilicon structure to form a P-doped polysilicon structure;

removing the first masking layer to expose the N area polysilicon structure;

forming a second masking layer over the P area polysilicon structure;

doping the unmasked N area polysilicon structure to form an N-doped polysilicon structure to complete fabrication of the doped polysilicon structures.

23. The method of claim 22, wherein the polysilicon structures are gates.

24. The method of claim 22, wherein the N-doped polysilicon structure is formed before the P-doped polysilicon structure.

25. The method of claim 22, wherein the substrate is a silicon substrate.

26. The method of claim 22, wherein the undoped polysilicon layer has a thickness of from about 1000 to 2500 Å

.

27. The method of claim 22, wherein the undoped polysilicon layer has a thickness of from about 1000 to 1500 Å

.

28. The method of claim 22, wherein the first and second masking layers are comprised of photoresist.

29. The method of claim 22, including the step of further processing the structure after formation of the P-doped and N-doped polysilicon structure.

30. The method of claim 22, including the steps of:

removing the first etched back first photoresist layer with the removal of the first masking layer;

forming a second photoresist layer over the substrate, covering and masking the N area undoped polysilicon structure and the P area P-doped polysilicon structure;

etching back the second photoresist layer to expose only the upper portions of the N area undoped polysilicon structure and the P area P-doped polysilicon structure;

then forming the second masking layer over the P area P-doped polysilicon structure and the etched back second photoresist layer only within the P area; and

then proceeding with the doping of the unmasked Narea polysilicon structure to complete fabrication of the doped polysilicon structures.

31. The method of claim 22, including the steps of:

removing the first etched back first photoresist layer with the removal of the first masking layer;

forming a second photoresist layer over the substrate, covering and masking the N area undoped polysilicon structure and the P area P-doped polysilicon structure;

etching back the second photoresist layer to expose only the upper portions of the N area undoped polysilicon structure and the P area P-doped polysilicon structure;

then forming the second masking layer over the P area P-doped polysilicon structure and the etched back second photoresist layer only within the P area; and

then proceeding with the doping of the unmasked N area polysilicon structure to complete fabrication of the doped polysilicon structures.

32. The method of claim 22, wherein the undoped polysilicon layer is patterned using an overlying patterned mask layer.

33. The method of claim 22, wherein the undoped polysilicon layer is patterned using an overlying patterned mask layer;

the overlying patterned mask layer being comprised of a material selected from the group consisting of photoresist, TEOS oxide, SiON and PEOX.

34. The method of claim 22, wherein the undoped polysilicon layer is patterned using an overlying patterned mask layer;

the overlying patterned mask layer being comprised of photoresist.