Forming electronic structures having dual dielectric thicknesses and the structure so formed

• US 6,566,191 B2
• Filed: 12/05/2000
• Issued: 05/20/2003
• Est. Priority Date: 12/05/2000
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Strub, Richard A., Hsu, Louis L., Tonti, William R., Radens, Carl J., Mandelman, Jack A.
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): Pham, Hoai
• Application Number:
  US09/731,148
• Publication Number:
  US 20020066916A1
• Time in Patent Office: 896 Days
• Field of Search: 438/243, 438/244, 438/246, 438/386, 438/387, 438/389, 257/68, 257/301
• US Class Current: 438/243
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H01L 29/945 Trench capacitors
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells

Abstract

A structure including a first device and a second device, wherein the second device has a dielectric thickness greater than the dielectric thickness of the first device, and the method of so forming the structure.

Claims

1. A method of forming first and second electronic devices comprising:

forming a first trench capacitor in a substrate, having a first surface dimension;

forming a second trench capacitor in said substrate, having a second surface dimension, wherein the second surface dimension is greater than the first surface dimension;

depositing a first dielectric having the first dielectric thickness within at least the first trench;

depositing a first material within the first and second trenches, wherein the first material substantially fills the first trench, and at least partially fills the second trench;

removing the first material from the second trench;

forming a second dielectric having the second dielectric thickness within the second trench; and

depositing a second material within the second trench.

2. The method of claim 1, wherein the substrate comprises a semiconductor wafer.

3. The method of claim 1, wherein the first and second materials are a material selected from the group consisting of:

amorphous silicon and polysilicon.

4. The method of claim 1, wherein removing the first material from the second trench comprises isotropically etching the first material within the second trench.

5. A method of forming first and second capacitors on a substrate, comprising the steps of:

etching first and second trenches in the substrate through a single mask;

forming a first capacitor in a first trench disposed in a first region of the substrate, said first capacitor having a given breakdown voltage and a first node dielectric; and

forming a second capacitor in a second trench disposed in a second region of the substrate, said second capacitor having a breakdown voltage greater than said first capacitor and a second node dielectric different from said first node dielectric.

6. The method of claim 5, wherein said step of etching said first and second trenches in said substrate comprises the steps of:

forming a mask layer over the substrate, said mask having a first opening of a first width and a second opening of a width greater than said first width; and

etching areas of the substrate exposed by the mask to form trenches, wherein a second trench formed in an area of the substrate beneath said second opening has a depth greater than a first trench formed in an area of the substrate beneath said first opening.

7. The method of claim 6, wherein a first capacitor is formed in said first trench and a second capacitor is formed in said second trench, said second capacitor having less capacitance per unit area than said first capacitor and having a greater total capacitance area than said first capacitor.

8. The method of claim 5, wherein an array capacitor is formed in said first trench and a decoupling capacitor is formed in said second trench.

9. The method of claim 5, wherein said first node dielectric is thinner than said second node dielectric.