Method for producing a cell of a semiconductor memory
First Claim
1. A method of producing a memory cell of a semiconductor memory, which comprises the following steps:
- providing a substrate;
forming a first trench in the substrate;
depositing a capacitor dielectric in the trench;
depositing a conductive trench fill in the trench;
sinking the conductive trench fill into the trench;
depositing a first insulating layer on the conductive trench fill in the trench;
overgrowing the first insulating layer epitaxially with an epitaxial layer, proceeding from the substrate;
forming a second trench in the epitaxial layer, the second trench extending through the first insulating layer to the conductive trench fill, and thereby removing a part of the substrate to the conductive trench fill, and forming a ridge from the epitaxial layer;
etching the first insulating layer, thereby undercutting the epitaxial layer;
depositing and sinking a contact layer, whereby the contact layer remains in an undercut region beneath the epitaxial layer;
depositing and sinking a second insulating layer in the second trench;
forming a gate oxide at the ridge;
forming lateral margin ridges as a gate on the gate oxide;
incorporating dopant into the ridge, thereby forming a doped region;
forming a bit line on the doped region;
forming a word line over the bit line; and
forming a word line contact for electrically connecting the gate to the word line.
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Accused Products
Abstract
The process first forms trench capacitors in a substrate, which are filled with a trench fill and in which a first insulating layer is disposed over the conductive trench fill. The first insulating layer is then overgrown laterally by a selectively grown epitaxial layer. The selective epitaxial layer is so structured that a ridge is formed from it. Next, the ridge is partially undercut, whereby the etch selectivity of the ridge relative to the first insulating layer is utilized for a wet-chemical etching procedure. Next, a contact layer is arranged in the undercut region, which connects the ridge and a transistor that has been formed in the ridge to the conductive trench fill. Lateral margin ridges are then formed next to the ridge as a gate, and a doped region is incorporated into the ridge as a source/drain zone of the transistor.
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Citations
9 Claims
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1. A method of producing a memory cell of a semiconductor memory, which comprises the following steps:
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providing a substrate;
forming a first trench in the substrate;
depositing a capacitor dielectric in the trench;
depositing a conductive trench fill in the trench;
sinking the conductive trench fill into the trench;
depositing a first insulating layer on the conductive trench fill in the trench;
overgrowing the first insulating layer epitaxially with an epitaxial layer, proceeding from the substrate;
forming a second trench in the epitaxial layer, the second trench extending through the first insulating layer to the conductive trench fill, and thereby removing a part of the substrate to the conductive trench fill, and forming a ridge from the epitaxial layer;
etching the first insulating layer, thereby undercutting the epitaxial layer;
depositing and sinking a contact layer, whereby the contact layer remains in an undercut region beneath the epitaxial layer;
depositing and sinking a second insulating layer in the second trench;
forming a gate oxide at the ridge;
forming lateral margin ridges as a gate on the gate oxide;
incorporating dopant into the ridge, thereby forming a doped region;
forming a bit line on the doped region;
forming a word line over the bit line; and
forming a word line contact for electrically connecting the gate to the word line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification
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- Resources
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Current AssigneePolaris Innovations Limited (Wi-LAN Inc.)
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Original AssigneeInfineon Technologies AG
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InventorsHofmann, Franz, Schlösser, Till
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Primary Examiner(s)Cao, Phat X.
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Assistant Examiner(s)Le, Thao X.
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Application NumberUS10/096,473Publication NumberTime in Patent Office434 DaysField of Search438/238, 438/245, 438/388, 438/242, 438/243, 438/250, 438/386, 438/399, 257/300, 257/301, 257/302, 257/67-71, 257/905-906, 257/908US Class Current438/245CPC Class CodesH10B 12/0383 wherein the transistor is v...H10B 12/053 the transistor being at lea...
