Salicided gate for virtual ground arrays

• US 6,566,194 B1
• Filed: 10/01/2001
• Issued: 05/20/2003
• Est. Priority Date: 10/01/2001
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Ramsbey, Mark T., Chang, Chi, Sun, Yu
• Primary Examiner(s): Ho, Hoai
• Assistant Examiner(s): TRAN, LONG K
• Application Number:
  US09/968,465
• Publication Number:
  US 20030085417A1
• Time in Patent Office: 596 Days
• Field of Search: 438/257, 438/275, 438/241, 438/299, 438/279, 438/776, 438/587, 257/324, 257/315
• US Class Current: 438/257
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/42 Simultaneous manufacture of periphery and memory cells
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

The present invention provides processes for doping and saliciding word lines in a virtual ground array flash memory device without causing shorting between bit lines. According to one aspect of the invention, word lines are doped prior to patterning the poly layer from which the word lines are formed in the core region. Thereby, the poly layer protects the substrate between the word lines from doping that could cause shorting between bit lines. According to another aspect of the invention, word lines are exposed while spacer material, dielectric, or like material protects the substrate between word lines. The spacer material or dielectric prevents the substrate from becoming salicided in a manner that, like doping, could cause shorting between bit lines. The invention provides virtual ground array flash memory devices with doped and salicided word lines, but no shorting between bit lines even in virtual ground arrays where there are no oxide island isolation regions between bit lines.

Claims

1. A method of forming a virtual ground array non-volatile semiconductor memory device, comprising:

providing a semiconductor substrate having a core region and a peripheral region, wherein oxide islands are not formed in the core region;

forming charge trapping layers comprising at least one dielectric layer over the core region;

forming a poly layer over at least the charge trapping layers;

prior to patterning the poly layer in the core region, doping the poly layer in the core region;

patterning the poly layer in the core region to form word lines;

masking the core region;

while the core region is masked and prior to saliciding the word lines, doping the substrate to form source and drain regions adjacent gates in the peripheral region; and

saliciding the word lines, wherein the source and drain regions adjacent the gates in the peripheral region are salicided at the same time as the word lines in the core region.

2. The method of claim 1, wherein the core region comprises buried bit lines.

3. The method of claim 2, wherein the virtual ground array non-volatile semiconductor memory device has a NOR device structure.

4. The method of claim 1, wherein the virtual ground array non-volatile semiconductor memory device comprises a SONOS memory device.

5. A method of forming a virtual ground array non-volatile semiconductor memory device, comprising:

providing a semiconductor substrate having a core region and a peripheral region, wherein oxide islands are not formed in the core region;

forming charge trapping layers comprising at least one dielectric layer over the core region;

forming a poly layer over at least the charge trapping layers;

patterning the poly layer in the core region to form word lines spaced apart on the substrate; and

saliciding the word lines, wherein the source and drain regions adjacent the gates in the peripheral region are salicided at the same time as the word lines in the core region.

6. The method of claim 5, wherein the core region comprises buried bit lines.

7. The method of claim 6, wherein the virtual ground array non-volatile semiconductor memory device has a NOR device structure.

8. The method of claim 5, wherein the virtual ground array non-volatile semiconductor memory device comprises a SONOS memory device.

9. The method of claim 5, wherein at least the dielectric layer protects the semiconductor substrate in the spaces between word lines from becoming salicided while the word lines are salicided.

10. The method of claim 5, wherein at least a layer of spacer material protects the semiconductor substrate in the spaces between word lines from becoming salicided while the word lines are salicided.