Method of forming an insulating layer in a trench isolation type semiconductor device
First Claim
1. A method of forming a trench-type device isolation layer, comprising:
- coating a polysilazane solution on a semiconductor substrate in a spin on glass (SOG) manner to form an SOG layer filling a trench formed in the semiconductor substrate for device isolation;
performing a thermal process for changing an upper portion of the SOG layer to a silicon oxide layer;
etching the thermally treated SOG layer to form a remaining SOG layer filling a predetermined portion of the trench, such that a top surface of the remaining SOG layer is recessed from a top surface of the semiconductor substrate by about 1000 Å
; and
stacking a CVD type silicon oxide layer on the remaining SOG layer to fill a remaining portion of the trench.
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Abstract
A method of forming a trench-type device isolation layer in which a trench is filled through two steps, wherein a polysilazane solution is coated on a semiconductor substrate, in which a trench for device isolation layer is formed, in a spin on glass (SOG) manner to form an SOG layer filling a predetermined portion of the trench. In order to maintain a conformal coating thickness without overfilling the trench, the polysilazane solution preferably has a solid-state perhydro polysilazane ([SiH2NH]n) of between about 5 to about 15 percent by weight. Following formation of the SOG layer, a subsequent annealing process is carried out. The SOG layer is etched to make a top surface of the remaining SOG layer recessed down to a degree of about 1000 Å from an inlet of the trench, and a remaining space of the trench is filled with an ozone TEOS USG layer or an HDP CVD layer.
110 Citations
14 Claims
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1. A method of forming a trench-type device isolation layer, comprising:
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coating a polysilazane solution on a semiconductor substrate in a spin on glass (SOG) manner to form an SOG layer filling a trench formed in the semiconductor substrate for device isolation;
performing a thermal process for changing an upper portion of the SOG layer to a silicon oxide layer;
etching the thermally treated SOG layer to form a remaining SOG layer filling a predetermined portion of the trench, such that a top surface of the remaining SOG layer is recessed from a top surface of the semiconductor substrate by about 1000 Å
; and
stacking a CVD type silicon oxide layer on the remaining SOG layer to fill a remaining portion of the trench.
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2. A method of forming a trench-type device isolation layer, comprising:
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coating a polysilazane solution on a semiconductor substrate in a spin on glass (SOG) manner to form an SOG layer filling a trench formed in the semiconductor substrate for device isolation, wherein a solid ingredient of the polysilazane solution is between about 5 to about 20 percent by weight and the SOG layer is coated on an active region around the trench to a thickness of about 500 Å
or less;
performing a thermal process for changing an upper portion of the SOG layer to a silicon oxide layer;
etching the thermally treated SOG layer to form a remaining SOG layer filling a predetermined portion of the trench; and
stacking a CVD type silicon oxide layer on the remaining SOG layer to fill a remaining portion of the trench. - View Dependent Claims (3, 4, 5, 6, 7)
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8. A method of forming a trench-type device isolation layer, comprising:
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stacking a pad oxide layer on a silicon substrate;
stacking a silicon nitride layer on the pad oxide layer;
patterning the silicon nitride layer to form a trench etch mask pattern;
etching the pad oxide layer and the substrate to form a trench for device isolation;
forming a thermal oxide layer on an inner wall of the trench such that the thermal oxide layer covers a bottom and sidewalls of the trench to a level that is even with the silicon nitride layer so that the trench has a convex portion that is an active region at the sidewall of the trench where the pad oxide layer meets the silicon nitride layer;
forming a silicon nitride liner on the entire substrate including the thermal oxide layer;
coating a polysilazane solution on the semiconductor substrate in a spin on glass (SOG) manner to form an SOG layer filling the trench formed in the semiconductor substrate for device isolation, wherein a solid ingredient of the polysilazane solution is between about 5 to about 20 percent by weight and the SOG layer is coated on the convex portion of the trench that is an active region to a thickness of about 500 Å
or less;
performing a thermal process for changing an upper portion of the SOG layer to a silicon oxide layer;
etching the thermally treated SOG layer to form a remaining SOG layer filling a predetermined portion of the trench;
stacking a CVD type silicon oxide layer on the remaining SOG layer to fill a remaining portion of the trench; and
removing the silicon nitride layer and pad oxide layer. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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Specification