Method of forming an insulating layer in a trench isolation type semiconductor device

• US 6,566,229 B2
• Filed: 11/26/2001
• Issued: 05/20/2003
• Est. Priority Date: 03/05/2001
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Heo, Jin-Hwa, Hong, Soo-Jin, Goo, Ju-Seon, Kim, Hong-Gun, Hong, Eun-Kee, Park, Moon-Han
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): MAI, ANH D
• Application Number:
  US09/991,928
• Publication Number:
  US 20020123206A1
• Time in Patent Office: 540 Days
• Field of Search: 438/424, 438/427, 438/435, 438/780, 438/781
• US Class Current: 438/435
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264

Abstract

A method of forming a trench-type device isolation layer in which a trench is filled through two steps, wherein a polysilazane solution is coated on a semiconductor substrate, in which a trench for device isolation layer is formed, in a spin on glass (SOG) manner to form an SOG layer filling a predetermined portion of the trench. In order to maintain a conformal coating thickness without overfilling the trench, the polysilazane solution preferably has a solid-state perhydro polysilazane ([SiH₂NH]n) of between about 5 to about 15 percent by weight. Following formation of the SOG layer, a subsequent annealing process is carried out. The SOG layer is etched to make a top surface of the remaining SOG layer recessed down to a degree of about 1000 Å from an inlet of the trench, and a remaining space of the trench is filled with an ozone TEOS USG layer or an HDP CVD layer.

Claims

1. A method of forming a trench-type device isolation layer, comprising:

coating a polysilazane solution on a semiconductor substrate in a spin on glass (SOG) manner to form an SOG layer filling a trench formed in the semiconductor substrate for device isolation;

performing a thermal process for changing an upper portion of the SOG layer to a silicon oxide layer;

etching the thermally treated SOG layer to form a remaining SOG layer filling a predetermined portion of the trench, such that a top surface of the remaining SOG layer is recessed from a top surface of the semiconductor substrate by about 1000 Å

; and

stacking a CVD type silicon oxide layer on the remaining SOG layer to fill a remaining portion of the trench.

2. A method of forming a trench-type device isolation layer, comprising:

coating a polysilazane solution on a semiconductor substrate in a spin on glass (SOG) manner to form an SOG layer filling a trench formed in the semiconductor substrate for device isolation, wherein a solid ingredient of the polysilazane solution is between about 5 to about 20 percent by weight and the SOG layer is coated on an active region around the trench to a thickness of about 500 Å

or less;

performing a thermal process for changing an upper portion of the SOG layer to a silicon oxide layer;

etching the thermally treated SOG layer to form a remaining SOG layer filling a predetermined portion of the trench; and

stacking a CVD type silicon oxide layer on the remaining SOG layer to fill a remaining portion of the trench.

3. The method as claimed in claim 2, wherein the subsequent thermal process consists of a bake process and an annealing process that is performed in a steam (H₂O)-supplied oxidation ambient at a temperature of between about 700°

C. to about 800°

C. for between about 10 to about 60 minutes.

4. The method as claimed in claim 2, wherein the polysilazane solution contains only a solid-state perhydro polysilazane ([SiH₂NH]n) of between about 5 to about 15 percent by weight.

5. The method as claimed in claim 2, wherein the CVD type silicon oxide layer is formed using a high density plasma (HDP) CVD.

6. The method as claimed in claim 5, further comprising planarizing the silicon oxide layer in a chemical mechanical polishing (CMP) manner after the formation thereof.

7. The method as claimed in claim 2, wherein the thermal process includes a bake process and an annealing process that is performed in a steam (H₂O) and a nitrogen (N₂)-supplied oxidation ambient at a temperature of between about 700°

C. to about 800°

C. for between about 10 to about 60 minutes.

8. A method of forming a trench-type device isolation layer, comprising:

stacking a pad oxide layer on a silicon substrate;

stacking a silicon nitride layer on the pad oxide layer;

patterning the silicon nitride layer to form a trench etch mask pattern;

etching the pad oxide layer and the substrate to form a trench for device isolation;

forming a thermal oxide layer on an inner wall of the trench such that the thermal oxide layer covers a bottom and sidewalls of the trench to a level that is even with the silicon nitride layer so that the trench has a convex portion that is an active region at the sidewall of the trench where the pad oxide layer meets the silicon nitride layer;

forming a silicon nitride liner on the entire substrate including the thermal oxide layer;

coating a polysilazane solution on the semiconductor substrate in a spin on glass (SOG) manner to form an SOG layer filling the trench formed in the semiconductor substrate for device isolation, wherein a solid ingredient of the polysilazane solution is between about 5 to about 20 percent by weight and the SOG layer is coated on the convex portion of the trench that is an active region to a thickness of about 500 Å

or less;

performing a thermal process for changing an upper portion of the SOG layer to a silicon oxide layer;

etching the thermally treated SOG layer to form a remaining SOG layer filling a predetermined portion of the trench;

stacking a CVD type silicon oxide layer on the remaining SOG layer to fill a remaining portion of the trench; and

removing the silicon nitride layer and pad oxide layer.

9. The method as claimed in claim 8, wherein the subsequent thermal process consists of a bake process and an annealing process that is performed in a steam (H₂O)-supplied oxidation ambient at a temperature of between about 700°

C. to about 800°

C. for between about 10 to about 60 minutes.

10. The method as claimed in claim 8, wherein the SOG layer is etched to make a top surface of the remaining SOG layer recessed from a top surface of the semiconductor substrate by about 1000 Å

.

11. The method as claimed in claim 8, wherein the polysilazane solution contains only a solid-state perhydro polysilazane ([SiH₂NH]n) of between about 5 to about 15 percent by weight.

12. The method as claimed in claim 8, wherein the CVD type silicon oxide layer is formed using a high density plasma (HDP) CVD.

13. The method as claimed in claim 12, further comprising planarizing the silicon oxide layer in a chemical mechanical polishing (CMP) manner after the formation thereof.

14. The method as claimed in claim 8, wherein the subsequent process includes a bake process and an annealing process that is performed in a steam (H₂O) and a nitrogen (N₂)-supplied oxidation ambient at a temperature of between about 700°

C. to about 800°

C. for between about 10 to about 60 minutes.