Power MOSFET cell with a crossed bar shaped body contact area

• US 6,566,710 B1
• Filed: 08/29/2001
• Issued: 05/20/2003
• Est. Priority Date: 08/29/2001
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Strachan, Andy, Brisbin, Douglas
• Primary Examiner(s): Cao, Phat X.
• Application Number:
  US09/942,480
• Time in Patent Office: 629 Days
• Field of Search: 257/331, 257/341, 257/401
• US Class Current: 257/341
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

The safe operating area of a high-voltage MOSFET, such as a lateral double-diffused MOS (LDMOS) transistor, is increased by using transistor cells with an X-shaped body contact region and four smaller source regions that adjoin the body contact region. The X-shaped body contact region lowers the parasitic base resistance of the transistor, thereby increasing the safe operating area of the transistor.

Claims

1. A transistor comprising:

a first region of semiconductor material having a first conductivity type and a first dopant concentration, the first region having a plurality of legs that extend away from a center region to form an X shape, the plurality of legs having ends;

a second region of semiconductor material having a second conductivity type and a second dopant concentration, the second region laterally contacting adjacent legs of the first region;

a third region of semiconductor material having the first conductivity type and a third dopant concentration that is less than the first dopant concentration, the third region laterally contacting the second region, and contacting the first region;

a fourth region of semiconductor material having the second conductivity type and a fourth dopant concentration, the fourth region laterally contacting the third region;

a fifth region of semiconductor material having the second conductivity type and a fifth dopant concentration, the fifth region lying laterally adjacent to the fourth region, being electrically connected to the fourth region and spaced apart from the second region, the fifth dopant concentration being substantially equivalent to the second dopant concentration;

a layer of isolation material formed on the third region; and

a gate segment formed on the layer of isolation material, the gate segment being straight and formed adjacent to the ends of the adjacent legs of the first region.

2. The transistor of claim 1 wherein the gate segment is formed over the adjacent legs of the first region.

3. The transistor of claim 2 wherein the layer of isolation material is also formed on a portion of the fourth region of semiconductor material, and the gate segment is also formed over the portion of the fourth region of semiconductor material.

4. The transistor of claim 2 and further comprising a region of field oxide formed between the fourth and fifth regions of semiconductor material.

5. The transistor of claim 1 wherein the second region has a substantially uniform dopant concentration.

6. The transistor of claim 1 and further comprising a sixth region of semiconductor material having the second conductivity type and a sixth dopant concentration that is less than the fifth dopant concentration, the sixth region lying below and contacting the fourth and fifth regions.