Circuit for protecting chips against IDD fluctuation attacks

• US 6,566,858 B1
• Filed: 07/10/1998
• Issued: 05/20/2003
• Est. Priority Date: 07/10/1998
• Status: Expired due to Term

• Current Assignee: Memjet Technology Ltd. (Memjet Limited)
• Original Assignee: Silverbrook Research Pty Limited
• Inventors: Silverbrook, Kia, Walmsley, Simon Robert
• Primary Examiner(s): Cuneo, Kamand
• Assistant Examiner(s): Nguyen, Jimmy
• Application Number:
  US09/112,763
• Time in Patent Office: 1,775 Days
• Field of Search: 324/763, 324/248, 324/613, 324/158.1, 733/79, 736/64, 731/16
• US Class Current: 361/100
• CPC Class Codes: H04L 2209/08 Randomization, e.g. dummy operations or using noise
• CPC Class Codes: H04L 2209/127 Trusted platform modules [TPM]
• CPC Class Codes: H04L 9/003 for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]

Abstract

A method of providing for resistance to attack by monitoring of an integrated circuit by means of monitoring I_dd current changes. The method comprises the step of including a spurious noise generation circuit as part of the integrated circuit, to increase the Signal to Noise Ratio in the I_dd signal and obscure meaningful information.

Claims

1. A method of providing for resistance to attack of an integrated circuit by means of monitoring current changes in a current signal in the integrated circuit, said method comprising the step of including as part of said integrated circuit a spurious electromagnetic noise generation circuit for emitting electromagnetic noise and reducing a Signal to Noise Ratio to obscure information in the current signal that is meaningful for the attack.

2. A method as claimed in claim 1 wherein said noise generation circuit comprises a random number generator.

3. A method as claimed in claim 2 wherein said random number generator comprises a LFSR (Linear Feedback Shift Register).

4. A method as claimed in claim 3 further including the step of clocking said LFSR at a maximum clock rate of the integrated circuit.

8. A method as claimed in claim 3 wherein a number of bits in the LFSR is comparable to other state changes in the integrated circuit that are to be protected from the attack.

5. An integrated circuit resistant to attack by monitoring current changes in a current signal in the integrated circuit the integrated circuit including a spurious electromagnetic noise generation circuit for emitting electromagnetic noise and decreasing a Signal to Noise Ratio to obscure information in the current signal that is meaningful for the attack.

6. An integrated circuit as claimed in claim 5 wherein said noise generation circuit comprises a random number generator.

7. An integrated circuit as claimed in claim 6 wherein said random number generator comprises a LFSR (Linear Feedback Shift Register).

9. An integrated circuit as claimed in claim 7 wherein a number of bits in the LFSR is comparable to other state changes in the integrated circuit that are to be protected from the attack.