Hysteretic self-biased amplifier

• US 6,566,926 B1
• Filed: 06/25/2002
• Issued: 05/20/2003
• Est. Priority Date: 06/25/2002
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Intel Corporation
• Inventors: Patterson, James D.
• Primary Examiner(s): TRAN, TOAN V
• Application Number:
  US10/179,003
• Time in Patent Office: 329 Days
• Field of Search: 327/65, 327/66, 327/67, 327/77, 327/205, 327/206, 327/68, 327/74, 330/253
• US Class Current: 327/206
• CPC Class Codes: H03F 3/345 with field-effect devices H03F3/347 takes precedence
• CPC Class Codes: H03F 3/45219 Folded cascode stages
• CPC Class Codes: H03F 3/4565 Controlling the common source circuit of the differential amplifier
• CPC Class Codes: H03F 3/45708 Controlling the common source circuit of the differential amplifier
• CPC Class Codes: H03K 3/02337 Bistables with hysteresis, e.g. Schmitt trigger non-regenerative amplitude discriminators G01R19/165
• CPC Class Codes: H03K 3/3565 Bistables with hysteresis, e.g. Schmitt trigger
• CPC Class Codes: H03K 5/2481 with at least one differential stage

Abstract

An amplifier and system includes hysteresis circuits.

Claims

1. A circuit comprising:

a first differential pair of input transistors coupled between a pair of output nodes and a first common node, the first differential pair of input transistors having control nodes coupled between a pair of input nodes;

a second differential pair of input transistors coupled between the pair of output nodes and a second common node, the second differential pair of input transistors having control nodes coupled between the pair of input nodes;

a first tail transistor coupled between the first common node and an upper voltage supply node;

a second tail transistor coupled between the second common node and a lower voltage supply node, wherein the first and second tail transistors are configured to be biased by one of the pair of output nodes;

an output sense hysteresis tuning circuit coupled between the pair of output nodes; and

an output switch hysteresis circuit coupled between the pair of output nodes.

2. The circuit of claim 1 wherein the output sense hysteresis tuning circuit comprises a first pair of complementary transistors coupled in series between the first common node and the second common node, the first pair of complementary transistors having control nodes coupled to a first output node of the pair of the output nodes, and having a node formed at a junction between the first pair of complementary transistors coupled to a second output node of the pair of output nodes.

3. The circuit of claim 2 wherein the output switch hysteresis circuit comprises a second pair of complementary transistors coupled in series between the first common node and the second common node, the second pair of complementary transistors having control nodes coupled to the second output node, and having a node formed at a junction between the second pair of complementary transistors coupled to the first output node.

4. The circuit of claim 3 wherein the first pair of complementary transistors are sized to provide hysteresis between the pair of input nodes and the pair of output nodes.

5. A self-biased amplifier circuit comprising:

a first tail transistor coupled to be biased by a first amplifier output node, the first tail transistor coupled to an upper voltage supply node;

a second tail transistor coupled to be biased by the first amplifier output node, the second tail transistor coupled to a lower voltage supply node;

an output sense hysteresis tuning circuit coupled between the first and second tail transistors, the output sense hysteresis tuning circuit configured to drive the first amplifier output node in response to a second amplifier output node; and

an output switch hysteresis circuit coupled between the first and second tail transistors, the output switch hysteresis circuit configured to drive the second amplifier output node in response to the first amplifier output node.

6. The self-biased amplifier circuit of claim 5 further comprising:

a first differential pair of input transistors having a common node coupled to the first tail transistor; and

a second differential pair of input transistors having a common node coupled to the second tail transistor.

7. The self-biased amplifier circuit of claim 6 wherein the first and second differential pairs of input transistors are coupled to form the first and second amplifier output nodes.

8. The self-biased amplifier circuit of claim 6 further comprising first and second cascode output stages coupled to the first and second differential pairs of input transistors.

9. The self-biased amplifier circuit of claim 6 further comprising a first feedback transistor coupled in series between the first tail transistor and the output sense hysteresis tuning circuit.

10. The self-biased amplifier circuit of claim 9 further comprising a common mode feedback circuit including a diode coupled between the upper voltage supply node and a control node of the first feedback transistor.

11. The self-biased amplifier circuit of claim 10 wherein the feedback circuit further includes:

a second diode coupled to the lower supply voltage node;

a first pair of complementary transistors coupled in series between the first and second diodes, the first pair of complementary transistors having control nodes coupled in common with an input node of the self-biased amplifier circuit; and

a second pair of complementary transistors coupled in series between the first and second diodes, the second pair of complementary transistors having control nodes coupled in common with a second input node of the self-biased amplifier circuit.

12. The self-biased amplifier circuit of claim 11 further comprising a second feedback transistor coupled in series between the second tail transistor and the output sense hysteresis tuning circuit, the second feedback transistor having a control node coupled to the second diode.

13. An apparatus comprising:

first and second tail transistors;

a hysteresis circuit;

a first feedback transistor coupled between the first tail transistor and the hysteresis circuit;

a second feedback transistor coupled between the second tail transistor and the hysteresis circuit; and

a feedback circuit to couple a control node of the first feedback transistor to an upper voltage supply node through a first diode, and to couple a control node of the second feedback transistor to a lower voltage supply node through a second diode.

14. The apparatus of claim 13 further comprising:

a first differential pair of input transistors coupled to the first tail transistor, the first differential pair of input transistors having control nodes coupled to a pair of differential input nodes.

15. The apparatus of claim 14 wherein the feedback circuit comprises:

a first pair of complementary transistors coupled in series between the first and second diodes, wherein control nodes of the first pair of complementary transistors are coupled to a first of the pair of differential input nodes.

16. The apparatus of claim 15 wherein the feedback circuit further comprises:

a second pair of complementary transistors coupled in series between the first and second diodes, wherein control nodes of the second pair of complementary transistors are coupled to a second of the pair of differential input nodes.

17. The apparatus of claim 13 wherein the hysteresis circuit comprises a first complementary pair of transistors coupled in series between the first and second feedback transistors.

18. The apparatus of claim 17 further comprising a second hysteresis circuit including a second complementary pair of transistors coupled in series between the first and second tail transistors.

19. The apparatus of claim 13 further comprising:

a first differential pair of input transistors coupled to the first tail transistor, the first differential pair of input transistors having control nodes coupled to a pair of differential input nodes;

a second differential pair of input transistors coupled to the second tail transistor, the second differential pair of input transistors having control nodes coupled to the pair of differential input nodes; and

a first cascode output stage and a second cascode output stage coupled to the first and second differential pairs of input transistors.

20. The apparatus of claim 19 wherein the first cascode output stage is configured to provide a self-bias node coupled to the first and second tail transistors.

21. The apparatus of claim 20 wherein the feedback circuit comprises:

a first pair of complementary transistors coupled in series between the first and second diodes, wherein control nodes of the first pair of complementary transistors are coupled to a first of the pair of differential input nodes.

22. The apparatus of claim 21 wherein the feedback circuit further comprises:

a second pair of complementary transistors coupled in series between the first and second diodes, wherein control nodes of the second pair of complementary transistors are coupled to a second of the pair of differential input nodes.

23. A system comprising:

a first tail transistor coupled to be biased by a first amplifier output node, the first tail transistor coupled to an upper voltage supply node;

a second tail transistor coupled to be biased by the first amplifier output node, the second tail transistor coupled to a lower voltage supply node;

an output sense hysteresis tuning circuit coupled between the first and second tail transistors, the output sense hysteresis tuning configured to drive the first amplifier output node in response to a second amplifier output node;

an output switch hysteresis circuit coupled between the first and second tail transistors, the output switch hysteresis circuit configured to drive the second amplifier output node in response to the first amplifier output node; and

a universal serial bus controller coupled to the second amplifier output node.

24. The system of claim 23 further comprising:

a first differential pair of input transistors having a common node coupled to the first tail transistor; and

a second differential pair of input transistors having a common node coupled to the second tail transistor.

25. The system of claim 24 wherein the first and second differential pairs of input transistors are coupled to form the first and second amplifier output nodes.

26. The system of claim 24 further comprising first and second cascode output stages coupled to the first and second differential pairs of input transistors.

27. The system of claim 24 further comprising a first feedback transistor coupled in series between the first tail transistor and the output sense hysteresis tuning circuit.

28. The system of claim 27 further comprising a common mode feedback circuit including a diode coupled between the upper voltage supply node and a control node of the first feedback transistor.

29. The system of claim 28 wherein the feedback circuit further includes:

a second diode coupled to the lower supply voltage node;

a first pair of complementary transistors coupled in series between the first and second diodes, the first pair of complementary transistors having control nodes coupled in common with an input node of the self-biased amplifier circuit; and

a second pair of complementary transistors coupled in series between the first and second diodes, the second pair of complementary transistors having control nodes coupled in common with a second input node of the self-biased amplifier circuit.