Wide-band single-ended to differential converter in CMOS technology

• US 6,566,961 B2
• Filed: 03/30/2001
• Issued: 05/20/2003
• Est. Priority Date: 03/30/2001
• Status: Active Grant

• Current Assignee: Institute of Microelectronics, Wipro Limited
• Original Assignee: Institute of Microelectronics, OKI Techno Centre Pte Limited
• Inventors: Dasgupta, Uday, Hwee, Teo Tian
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): NGUYEN, KHAI M
• Application Number:
  US09/821,511
• Publication Number:
  US 20020175763A1
• Time in Patent Office: 781 Days
• Field of Search: 330/253, 330/257, 330/301
• US Class Current: 330/301
• CPC Class Codes: H03F 2203/45508 the CSC comprising a voltage generating circuit as bias circuit for the CSC
• CPC Class Codes: H03F 2203/45544 the IC comprising one or more capacitors, e.g. coupling capacitors
• CPC Class Codes: H03F 2203/45562 the IC comprising a cross coupling circuit, e.g. comprising two cross-coupled transistors
• CPC Class Codes: H03F 2203/45631 the LC comprising one or more capacitors, e.g. coupling capacitors
• CPC Class Codes: H03F 2203/45702 the LC comprising two resistors
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence

Abstract

A wide-band single-ended to differential converter (DC to 1 GHz) with very low amplitude and phase matching errors, of the order of 0.01 dB and 0.15 degrees respectively and using CMOS technology, is comprised of a first and a second stage. The very low amplitude and phase matching errors have been achieved firstly by the use of capacitive means C_D across the gate and source of the first stage MOS transistor M₁ with a value equal to the drain to ground (reference potential) parasitic capacitance of the tail current source device for the first stage, and secondly by using equal valued capacitive means C_F1, C_F2 in the second stage and setting their values to be several (5-10) times more than the gate-drain parasitic capacitances of either of the differential transistors of the second stage.

Claims

1. A circuit for converting a single-ended input signal to a differential output signal, comprising:

a voltage supply;

a reference potential;

a first stage, having an input INP and a bias input IBIAS, first and second output nodes N1 and N2, said first stage providing a differential output signal at said nodes N1 and N2, said first stage having a first and a second MOS transistor of a first conductivity-type forming a differential amplifier, a first and a second resistive means connected between said voltage supply and the drain of said first and said second MOS transistor, respectively, where the drains of said first and said second MOS transistor represent said first and said second output node N1 and N2, respectively, the gate of said first MOS transistor connected to said input INP via capacitive means C_I, and where a capacitive means C_D connected across said gate and a source of said first MOS transistor compensates for a parasitic drain to reference potential capacitance C_B of a tail current source; and

a second stage connected to said nodes N1 and N2, said second stage having a third and a fourth MOS transistor of said first conductivity-type forming a differential amplifier, where gates of said third and said fourth MOS transistors are connected to said nodes N1 and N2, respectively, where a third and a fourth resistive means are connected between said voltage supply and the drain of said third and said fourth MOS transistor, respectively, said second stage having outputs OUTA and OUTB coupled to the drains of said third and said fourth MOS transistor, respectively, said outputs OUTA and OUTB providing fully differential, wide-band signals ranging in frequency from 100 kHz to 1 GHz (1 GHz=10⁹ Hertz), with a magnitude and phase error at said frequency of 1 GHz, when referenced to a signal at said input INP, of no more than 0.015 dB (10 dB=1 Bell) and 0.15 degrees, respectively.

2. The circuit of claim 1, wherein said bias input IBIAS is the input to a current source for providing current to first and second current mirrors.

3. The circuit of claim 2, wherein said first mirror is connected between the junction of the sources of said first and said second MOS transistors and said reference potential.

4. The circuit of claim 1, wherein said capacitive means C_D splits the input voltage at said input INP equally across the gate-source of said first and said second MOS transistor.

5. The circuit of claim 1, wherein said second stage is further comprised of a second current mirror connected between the junction of the sources of said third and said fourth MOS transistors and said reference potential.

6. The circuit of claim 1, wherein said second stage is further comprised of a first capacitive means C_F1 and a second capacitive means C_F2, where said capacitive means C_F1 and C_F2 are connected between the drain of said third and said fourth MOS transistors and the gate of said fourth and said third MOS transistor, respectively.

7. The circuit of claim 6, wherein said first and said second capacitive means C_F1 and C_F2, where said capacitive means C_F1 and C_F2 each have a capacitance 5 to 10 times larger than the parasitic gate-to-drain capacitance of said third and said fourth MOS transistor, respectively.

8. A circuit for converting a single-ended input signal to a differential output signal, comprising:

a voltage supply;

a reference potential;

a first stage, having an input INP with signal v_i and a bias input IBIAS with signal ibias, first and second output nodes N1 and N2 with signals v_i1 and v_i2, respectively, said first stage providing a differential output signal at said nodes N1 and N2, said first stage having a first and a second MOS transistor of a first conductivity-type forming a differential amplifier, a first and a second resistive means connected between said voltage supply and the drain of said first and said second MOS transistor, respectively, the gate of said first MOS transistor coupled to said input INP via capacitive means C_I1, and where a capacitive means C_D connected across said gate and the source of said first MOS transistor compensates for a parasitic drain to reference potential capacitance C_B of a tail current source, where said first stage further comprises;

a current source having an input and a first and a second output, said input of said current source coupled to said bias input IBIAS for biasing said current source, said current source comprised of MOS transistors of a second conductivity-type;

a first and a second current mirror, with a first and a second input each, said first and said second input of said current mirrors connected to said first and said second output of said current source, respectively, said first and said second current mirror comprised of MOS transistors of a said first conductivity-type;

the drains of said first and said second MOS transistor coupled to said voltage supply via said first and said second resistive means, respectively;

the drains of said first and said second MOS transistors labeled nodes N1 and N2, respectively;

the sources of said first and said second MOS transistor joined in node T1 and coupled via said first current mirror to said reference potential;

a fifth resistive means in series with said second current mirror coupled between said voltage supply and said reference potential;

the gate of said first and said second MOS transistor coupled via a sixth and a seventh resistive means, respectively, to the junction between said fifth resistive means and said second current mirror; and

the gate of said second MOS transistor coupled via capacitive means C_I2 to said reference potential;

a second stage connected to said nodes N1 and N2, said second stage having outputs OUTA and OUTB, said second stage having a third and a fourth MOS transistor of said first conductivity-type forming a differential amplifier, a first capacitive means C_F1 connected between the drain of said third MOS transistor and the gate of said fourth MOS transistor, a second capacitive means C_F2 connected between the drain of said fourth MOS transistor and the gate of said third MOS transistor, said first and said second capacitive means C_F1 and C_F2 each having a capacitance 5 to 10 times larger than the parasitic gate-to-drain capacitance of said third and said fourth MOS transistor, respectively, said first and second capacitive means C_F1 and C_F2 contributing toward a frequency response of signals v_o1 and v_o2 at said outputs OUTA and OUTB, ranging in frequency from 100 kHz to 1 GHz (1 GHz=10⁹ Hertz), with a magnitude and phase error at said frequency of 1 GHz of no more than 0.015 dB (10 dB=1 Bell) and 0.15 degrees, respectively, when referenced to said signal v_i at said input INP; and

said first and said second stage connected between said voltage supply and said reference potential.

9. The circuit of claim 8, wherein said first and second current mirrors are cascoded current mirrors.

10. The circuit of claim 8, wherein said second stage further comprises:

a current source having an input and a first and a second output, said input of said current source coupled to said bias input IBIAS for biasing said current source, said current source comprised of MOS transistors of a second conductivity-type;

a current mirror, with a first and a second input, said first and said second input of said current mirror connected to said first and said second output of said current source, respectively, said current mirror comprised of MOS transistors of a said first conductivity-type;

the drains of said third and said fourth MOS transistor coupled to said voltage supply via said third and said fourth resistive means, respectively;

the drains of said third and said fourth MOS transistors representing outputs OUTA and OUTB, respectively;

the sources of said third and said fourth MOS transistor joined in node T2 and coupled via said to said reference potential; and

the gate of said third and said fourth MOS transistor connected to said node N1 and N2, respectively.

11. The circuit of claim 10, wherein said current mirror is a cascoded current mirror.

12. The circuit of claim 8, wherein the magnitude of gain at said outputs OUTA and OUTB ranges from 7 to 9 dB (10 dB=1 Bell) at a frequency of 100 kHz (1 kHz=1000 Hertz).

13. The circuit of claim 8, wherein the magnitude of gain at said outputs OUTA and OUTB ranges from 6 to 8 dB at a frequency of 1 GHz (1 GHz=109 Hertz).

14. The circuit of claim 8, wherein the phase of gain at said output OUTA is less than 0.09 degrees at a frequency of 100 kHz (1 kHz=1000 Hertz).

15. The circuit of claim 8, wherein the phase of gain at said output OUTA is less than −

72 degrees at a frequency of 1 GHz (1 GHz=109 Hertz).

16. The circuit of claim 8, wherein the phase of gain at said output OUTB is at least −

179 degrees at a frequency of 100 kHz (1 kHz=1000 Hertz).

17. The circuit of claim 8, wherein the phase of gain at said output OUTB is at least 108 degrees at a frequency of 1 GHz (1 GHz=10⁹ Hertz).

18. The circuit of claim 8, wherein said capacitive means C_D splits the input voltage at said input INP equally across the gate-source of said first and said second MOS transistor.

19. A method of converting a single-ended input signal to a differential output signal, comprising:

providing a differential input stage, having a signal input INP and differential output signals;

providing differential amplification in said differential input stage with a first and a second MOS transistor, where said first MOS transistor receives said signal input INP;

compensating a parasitic tail current source transistor capacitance of said differential input stage with capacitive means C_D connected across the gate and a source of said first MOS transistor thereby splitting the input signal voltage equally across the gate-source of said first and said second MOS transistor;

connecting a differential output stage to said differential output signals of said input stage;

providing said differential amplification of said differential output stage with a third and a fourth MOS transistor;

coupling compensating capacitive means between the gates of one of said transistors of said differential output stage with the drains of the other transistor of said output stage;

making the capacitance of said compensating capacitive means from 5 to 10 times larger than the parasitic capacitance from gate-source of said transistors of said differential output stage to compensate for negative feedback effects;

making the transconductance of said transistors of said differential output stage larger by a factor ranging from 40 to 100 than the output conductance of the tail current source transistor of said differential output stage; and

providing fully differential output signals at the output of said differential output stage ranging in frequency from 100 kHz to 1 GHz (1 GHz=10⁹ Hertz), with a magnitude and phase error at said frequency of 1 GHz of no more than 0.015 dB (10 dB=1 Bell) and 0.15 degrees, respectively, when referenced to an signal at said input INP.