Frequency synthesizer and oscillation frequency control method

• US 6,566,964 B1
• Filed: 10/26/2000
• Issued: 05/20/2003
• Est. Priority Date: 10/29/1999
• Status: Expired due to Fees

• Current Assignee: Filtronic Comtek (UK) Ltd. (Filtronic Plc)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Hirano, Shunsuke
• Primary Examiner(s): KINKEAD, ARNOLD M
• Application Number:
  US09/696,031
• Time in Patent Office: 936 Days
• Field of Search: 331/1.A, 331/16, 331/25, 377/48, 327/156, 327/159, 455/260, 708/271
• US Class Current: 331/1.00A
• CPC Class Codes: H03B 21/02 by plural beating, i.e. for frequency synthesis ; Beating in combination with multiplication or division of frequency digital frequency synthesis using a ROM G06F1/02; digital frequency synthesis in general H03K; indirect frequency synthesis using a PLL H03L7/16
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider

Abstract

Accumulator 201 accumulates data K (K: integer) for every clock and outputs a carry-out signal at the time of an overflow. Random signal generator 202 outputs a random signal for every clock. Adder 203 adds the carry-out signal and random signal to data M (M: integer), changes the frequency dividing ratio randomly and converts spurious to white noise. This makes it possible to optimally maintain the spurious characteristic, shorten the lockup time and reduce power consumption.

Claims

1. A frequency synthesizer, comprising:

a voltage control oscillator that provides a second signal of a frequency corresponding to a voltage of a previously generated first signal;

a first frequency divider that divides the frequency of said second signal and outputs a third signal;

a second frequency divider that divides the frequency of a reference signal and outputs a fourth signal;

a phase comparator that generates the first signal from the phase difference between said third signal and said fourth signal and outputs the first signal to said voltage control oscillator; and

a frequency dividing ratio controller that controls a frequency dividing ratio so that the frequency dividing ratio changes substantially randomly with time and an average value of the frequency dividing ratio includes decimals, wherein the frequency dividing ratio controller comprises;

an accumulator that generates a carry-out signal when an accumulated value of first input data exceeds a predetermined value;

a random signal generator that generates a random signal whose value changes substantially randomly;

a bit length controller that variably controls the bit length of the random signal; and

an adder that adds said carry-out signal and said random signal to second input data and outputs the addition result of said adder as the frequency dividing ratio.

2. The frequency synthesizer according to claim 1, wherein the frequency dividing ratio controller comprises a plurality of random signal generators, which each have different bit lengths, and the bit length controller selects one of said plurality of random signal generators and distributes a clock signal to the selected random signal generator.

3. The frequency synthesizer according to claim 1, wherein the bit length controller variably controls the bit length of the random signal based on the frequency of the second signal of the voltage control oscillator.

4. The frequency synthesizer according to claim 1, wherein the bit length controller variably controls the bit length of the random signal using transmission time slots and reception time slots.

17. The frequency synthesizer according to claim 1, wherein said frequency dividing ratio controller includes said bit length controller.

5. A frequency synthesizer, comprising:

a voltage control oscillator that provides a second signal of a frequency corresponding to a voltage of a previously generated first signal;

a first frequency divider that divides the frequency of said second signal and outputs a third signal;

a second frequency divider that divides the frequency of a reference signal and outputs a fourth signal;

a phase comparator that generates the first signal from the phase difference between said third signal and said fourth signal and outputs the first signal to said voltage control oscillator; and

a frequency dividing ratio controller that controls a frequency dividing ratio so that the frequency dividing ratio changes substantially randomly with time and an average value of the frequency dividing ratio includes decimals, wherein the frequency dividing ratio controller comprises;

an accumulator that generates a carry-out signal when an accumulated value of first input data exceeds a predetermined value;

a random signal generator that generates a random signal whose value changes substantially randomly; and

an adder that adds said carry-out signal and said random signal to second input data and outputs the addition result of said adder as the frequency dividing ratio,

wherein the frequency dividing ratio controller outputs the frequency dividing ratio to the first frequency divider and said first frequency divider divides the frequency of the second signal with the frequency dividing ratio output from said frequency dividing ratio controller.

6. A frequency synthesizer, comprising:

a voltage control oscillator that provides a second signal of a frequency corresponding to a voltage of a previously generated first signal;

a first frequency divider that divides the frequency of said second signal and outputs a third signal;

a second frequency divider that divides the frequency of a reference signal and outputs a fourth signal;

a phase comparator that generates the first signal from the phase difference between said third signal and said fourth signal and outputs the first signal to said voltage control oscillator; and

a frequency dividing ratio controller that controls a frequency dividing ratio so that the frequency dividing ratio changes substantially randomly with time and an average value of the frequency dividing ratio includes decimals, wherein the frequency dividing ratio controller comprises;

an accumulator that generates a carry-out signal when an accumulated value of first input data exceeds a predetermined value;

a random signal generator that generates a random signal whose value changes substantially randomly; and

an adder that adds said carry-out signal and said random signal to second input data and outputs the addition result of said adder as the frequency dividing ratio,

wherein the frequency dividing ratio controller outputs the frequency dividing ratio to the second frequency divider and said second frequency divider divides the frequency of the reference signal with the frequency dividing ratio output from said frequency dividing ratio controller.

7. The frequency synthesizer according to claim 6, wherein the first frequency divider comprises a plurality of cascaded frequency dividers.

8. A base station apparatus equipped with a frequency synthesizer, said frequency synthesizer comprising:

a voltage control oscillator that provides a second signal of a frequency corresponding to a voltage of a previously generated first signal;

a first frequency divider that divides the frequency of said second signal and outputs a third signal;

a second frequency divider that divides the frequency of a reference signal and outputs a fourth signal;

a phase comparator that generates the first signal from the phase difference between said third signal and said fourth signal and outputs the first signal to said voltage control oscillator;

an accumulator that generates a carry-out signal when an accumulated value of first input data exceeds a predetermined value;

a random signal generator that generates a random signal whose value changes substantially randomly;

a bit length controller that variably controls the bit length of the random signal; and

an adder that adds said carry-out signal and said random signal to second input data and outputs the addition result of said adder as a frequency dividing ratio.

9. A communication terminal apparatus equipped with a frequency synthesizer, said frequency synthesizer comprising:

a voltage control oscillator that provides a second signal of a frequency corresponding to a voltage of a previously generated first signal;

a first frequency divider that divides the frequency of said second signal and outputs a third signal;

a second frequency divider that divides the frequency of a reference signal and outputs a fourth signal;

a phase comparator that generates the first signal from the phase difference between said third signal and said fourth signal and outputs the first signal to said voltage control oscillator;

an accumulator that generates a carry-out signal when an accumulated value of first input data exceeds a predetermined value;

a random signal generator that generates a random signal whose value changes substantially randomly;

a bit length controller that variably controls the bit length of the random signal; and

an adder that adds said carry-out signal and said random signal to second input data and outputs the addition result of said adder as a frequency dividing ratio.

10. A frequency dividing ratio control method, comprising:

generating a carry-out signal when an accumulated value of first input data exceeds a predetermined value;

generating a random signal whose value changes substantially randomly;

variably controlling the bit length of the random signal; and

generating a frequency dividing ratio by adding said carry-out signal and said random signal to second input data.

11. An oscillation frequency control method comprising the steps of:

oscillating a second signal of a frequency corresponding to a voltage of a first signal;

outputting a third signal by dividing the frequency of said second signal based on the frequency dividing ratio generated using the frequency dividing ratio control method according to claim 10,

outputting a fourth signal by dividing the frequency of a reference signal based on a fixed frequency dividing ratio; and

generating said first signal from the phase difference between said third signal and said fourth signal.

12. An oscillation frequency control method comprising:

oscillating a second signal of a frequency corresponding to a voltage of a first signal;

outputting a third signal by dividing the frequency of said second signal based on a fixed frequency dividing ratio;

outputting a fourth signal by dividing the frequency of a reference signal based on the frequency dividing ratio generated using the frequency dividing ratio control method according to claim 10; and

generating a next first signal from the phase difference between said third signal and said fourth signal.

13. A frequency synthesizer, comprising:

a voltage control oscillator that provides a second signal of a frequency corresponding to a voltage of a previously generated first signal;

a first frequency divider that divides the frequency of said second signal and outputs a third signal;

a second frequency divider that divides the frequency of a reference signal and outputs a fourth signal;

a phase comparator that generates the first signal from the phase difference between said third signal and said fourth signal and outputs the first signal to said voltage control oscillator; and

a frequency dividing ratio controller that controls a frequency dividing ratio so that the frequency dividing ratio changes substantially randomly with time and an average value of the frequency dividing ratio includes decimals, wherein the frequency dividing ratio controller comprises;

an accumulator that generates a carry-out signal when an accumulated value of first input data exceeds a predetermined value;

a random signal generator that generates a random signal whose value changes substantially randomly; and

an adder that adds said carry-out signal and said random signal to second input data and outputs the addition result of said adder as the frequency dividing ratio,

wherein said adder does not add a contribution from said first input data to the frequency dividing ratio, except as said first input data is accumulated into said carry-out data by said accumulator.

14. A base station apparatus equipped with a frequency synthesizer, said frequency synthesizer comprising:

a voltage control oscillator that provides a second signal of a frequency corresponding to a voltage of a previously generated first signal;

a first frequency divider that divides the frequency of said second signal and outputs a third signal;

a second frequency divider that divides the frequency of a reference signal and outputs a fourth signal;

a phase comparator that generates the first signal from the phase difference between said third signal and said fourth signal and outputs the first signal to said voltage control oscillator;

an accumulator that generates a carry-out signal when an accumulated value of first input data exceeds a predetermined value;

a random signal generator that generates a random signal whose value changes substantially randomly; and

an adder that adds said carry-out signal and said random signal to second input data and outputs the addition result of said adder as a frequency dividing ratio,

wherein said adder does not add a contribution from said first input data to the frequency dividing ratio, except as said first input data is accumulated into said carry-out data by said accumulator.

15. A communication terminal equipped with a frequency synthesizer, said frequency synthesizer comprising:

a voltage control oscillator that provides a second signal of a frequency corresponding to a voltage of a previously generated first signal;

a first frequency divider that divides the frequency of said second signal and outputs a third signal;

a second frequency divider that divides the frequency of a reference signal and outputs a fourth signal;

a phase comparator that generates the first signal from the phase difference between said third signal and said fourth signal and outputs the first signal to said voltage control oscillator;

an accumulator that generates a carry-out signal when an accumulated value of first input data exceeds a predetermined value;

a random signal generator that generates a random signal whose value changes substantially randomly; and

an adder that adds said carry-out signal and said random signal to second input data and outputs the addition result of said adder as a frequency dividing ratio,

wherein said adder does not add a contribution from said first input data to the frequency dividing ratio, except as said first input data is accumulated into said carry-out data by said accumulator.

16. A frequency dividing ratio control method comprising generating a carry-out signal when an accumulated value of first input data exceeds a predetermined value, generating a random signal whose value changes substantially randomly, and generating a frequency dividing ratio by adding said carry-out signal and said random signal to second input data, wherein said frequency dividing ratio does not include a contribution from said first input data, except as said first input data is accumulated into said carry-out data.