Method and apparatus for capturing video files for use in HDTV broadcast and demonstration

• US 6,567,130 B1
• Filed: 03/30/2000
• Issued: 05/20/2003
• Est. Priority Date: 03/30/2000
• Status: Expired due to Fees

• Current Assignee: US Bank National Association As Administrative Agent For The Lenders
• Original Assignee: Sencore Incorporated (Wellav Technologies Ltd.)
• Inventors: Schulz, Rod A.
• Primary Examiner(s): HSIA, SHERRIE Y
• Application Number:
  US09/538,835
• Time in Patent Office: 1,146 Days
• Field of Search: H04/N.964, 348/714, 348/715, 348/716, 348/718, 348/719, 345/558
• US Class Current: 348/714
• CPC Class Codes: H04N 5/781 on disks or drums
• CPC Class Codes: H04N 9/8042 involving data reduction

Abstract

A method and apparatus are disclosed for capturing and storing digital high definition television signals. The signals are taken from an input device in 8-bit parallel fashion at a constant flow rate and put into each of four 8-bit first in-first out memory registers until they are half full. After the respective first in-first out memory registers are half filled, additional quantities of data equal to half filling the registers are added while the data from the first half register filling is presented to the system memory as 32 bit words. That data is filled into a first of two concurrent blocks of system memory and after the first block is filled, while the second block is filled, the data is written from the first of the two concurrent blocks into another part of the system memory. The transfer of the 32-bit data words is accomplished at a faster rate than the input rate of the 8-bit data.

Claims

1. A method of capturing and storing digital HDTV signals comprising the steps of:

filling each of four first in-first out registers with data in an 8-bit per device sequential fashion at a constant flow rate until they are half full,

transferring said data to system memory as 32 bit words,

filling each of said four first in-first out registers with said data in an 8-bit per device sequential fashion at a constant flow rate in a quantity equal to half filling said first in-first out registers,

transferring said data to system memory as 32 bit words,

filling a first of 2 concurrent blocks of system memory with said data presented to said system memory,

filling a second of 2 concurrent blocks of system memory with said data presented to said system memory,

writing said data from said first of 2 concurrent blocks of system memory as said second of 2 concurrent blocks of system memory is filling,

writing said data from said second of 2 concurrent blocks of system memory as said first of 2 concurrent blocks of system memory is filling, and

the transfer of said 32 bit data words being accomplished at a faster rate than the input of said 8-bit data.

2. The method as called for in claim 1 wherein said constant flow rate of data into the first in-first out registers is 19.392658 megabits per second.

3. The method as called for in claim 1 wherein said constant flow rate of data into the first in-first out register is 2.424082 megabytes per second.

4. A data capturing and storage apparatus for storing 32 bit HDTV video data, said apparatus comprising:

a central processing unit,

system memory in communication with said central processing unit including at least first and second distinct blocks of memory,

four first in-first out registers set up in parallel relation,

a bus master, and

bus master control means for utilizing each of said first in-first out registers in half sections, and filling each half section sequentially.

5. The data capturing and storage apparatus as called for in claim 4 further including an input device.

6. The data capturing and storage apparatus as called for in claim 5 wherein said input device is an 8VSB demodulator.

7. The data capturing and storage apparatus as called for in claim 5 wherein said input device is a QPSK capture card for satellite downloads.

8. The data capturing and storage apparatus as called for in claim 5 wherein said input device is a DVD player.

9. The data capturing and storage apparatus as called for in claim 5 wherein said input device includes a parallel output that supports at lease one of TTL and LVDS signals.

10. The data capturing and storage apparatus as called for in claim 5 further including means for transferring data between said four first in-first out registers and said distinct blocks of system memory at a faster rate than an input of data from said inputs device to said four first in-first out registers.

11. The data capturing and storage apparatus as called for in claim 4 including means for re-clocking said data from a fixed rate standard for each input port of said sections on said four first in-first out registers.