Method for assembling a tiled, flat-panel microdisplay array having imperceptible seams

• US 6,567,138 B1
• Filed: 06/21/2000
• Issued: 05/20/2003
• Est. Priority Date: 02/15/1999
• Status: Expired due to Term

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Rainbow Displays, Inc.
• Inventors: Seraphim, Donald P., Krusius, J. Peter
• Primary Examiner(s): Parker, Kenneth
• Assistant Examiner(s): QI, ZHI QIANG
• Application Number:
  US09/597,661
• Time in Patent Office: 1,063 Days
• Field of Search: 349/73, 349/74, 349/153, 349/155, 349/158, 349/45, 349/122, 349/20, 349/21, 349/190, 349/103
• US Class Current: 349/73
• CPC Class Codes: G02F 1/13336 Combining plural substrates to produce large-area displays, e.g. tiled displays
• CPC Class Codes: G02F 1/136277 formed on a semiconductor substrate, e.g. of silicon

Abstract

This invention describes fabrication techniques for producing microdisplays suitable for combining into tiled, flat-panel displays having visually imperceptible seams. Assembly techniques to overcome flatness requirements imposed by tiled, flat-panel display assemblies are also described. Edge treatment techniques for individual microdisplays while still part of the silicon die or wafer are also described. The use of these inventive techniques allows the assembly microdisplays into tiled, flat-panel that are appear visually seamless and optically uniform.

Claims

1. A method for fabricating reflective microdisplay tiles for use in a tiled microdisplay, the projected image of said microdisplay having visually imperceptible seams, the steps comprising:

a) fabricating a plurality of reflective microdisplay tiles on a silicon wafer, each comprising a silicon substrate, a plurality of metallization layers, a plurality of insulating layers and a plurality of silicon layers, said substrate having an embedded integrated circuit backplane, each of said plurality of microdisplay tiles comprising pixel electrodes arranged in a substantially rectangular array and having a substantially uniform pixel pitch therebetween, said plurality of reflective microdisplay tiles having spaces therebetween;

b) conforming said spaces between said reflective microdisplay tiles to predetermined geometries to facilitate formation of precision edges thereupon to facilitate assembly of said reflective microdisplay tiles into said tiled microdisplay; and

c) microseparating said reflective microdisplay tiles along predetermined lines in said spaces thereby forming individual, fully functional reflective microdisplay tiles having precision edges adapted for forming tiled, reflective displays such that, when assembled into a tiled display, adjacent edge pixels of each of two abutting reflective microdisplay tiles have a pixel pitch therebetween substantially identical to said intra-microdisplay tile pixel pitch.

2. The method for fabricating microdisplay tiles for use in a tiled microdisplay as recited in claim 1, wherein said microseparating step (c) comprises etching.

3. The method for fabricating microdisplay tiles for use in a tiled microdisplay as recited in claim 2, wherein said etching step comprises the sub-step of one of the set of:

applying an etch mask to said silicon wafer, surface lithography, etching by anisotropic plasma, anisotropic wet etching, etching by reactive ion etching, and deep silicon etching.

4. The method for fabricating microdisplay tiles for use in a tiled microdisplay as recited in claim 3, wherein said deep silicon etch results in a etch substantially through said silicon wafer, resulting in said microseparating step (c) whereby said microdisplay tiles are separated one from another.

5. The method for fabricating microdisplay tiles for use in a tiled microdisplay as recited in claim 2, wherein said etching comprises a partial depth silicon etch.

6. The method for fabricating microdisplay tiles for use in a tiled microdisplay as recited in claim 5, wherein said microseparating step (c) comprises severing said microdisplays from one another in the region of said partial depth silicon etch.

7. The method for fabricating microdisplay tiles for use in a tiled microdisplay as recited in claim 2, wherein said silicon wafer comprises a crystalline silicon wafer having at least [100] and [111] crystalline planes, said planes determining the anisotropic wet etch rate.

8. The method for fabricating microdisplay tiles for use in a tiled microdisplay as recited in claim 2, wherein said etching results in a V-groove geometry in said seam region.

9. The method for fabricating microdisplay tiles for use in a tiled microdisplay as recited in claim 2, wherein said etching comprises a combination of back side and front side etches.

10. The method for fabricating microdisplay tiles for use in a tiled microdisplay as recited in claim 1, wherein said microseparating step (c) comprises at least one from the group of cleaving, severing, edge finishing, sawing, scribing and breaking.

11. The method for fabricating microdisplay tiles for use in a tiled microdisplay as recited in claim 1, further comprising the step of:

placing a mask proximate one of the major surfaces of said LCD glass cover plate.

12. The method for fabricating microdisplay tiles for use in a tiled microdisplay as recited in claim 1, further comprising the step of:

placing a mask on said seam between said microdisplay tiles.