Nonvolatile memory system, semiconductor memory, and writing method

• US 6,567,311 B2
• Filed: 03/13/2002
• Issued: 05/20/2003
• Est. Priority Date: 07/09/1996
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd., Hitachi ULSI Engineering Corp
• Inventors: Ishii, Tatsuya, Tsuchiya, Osamu, Miwa, Hitoshi, Kubono, Shooji
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): NGUYEN, HIEN N
• Application Number:
  US10/095,565
• Publication Number:
  US 20020136056A1
• Time in Patent Office: 433 Days
• Field of Search: 365/185.24, 365/185.18, 365/185.22, 365/185.29, 365/185.33, 365/185.3, 365/185.23
• US Class Current: 365/185.24
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2216/18 Flash erasure of all the cells in an array, sector or block simultaneously

Abstract

A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.

Claims

1. A nonvolatile memory device comprising:

a latch circuit;

a memory array; and

a controller,

wherein said controller is capable of receiving a plurality of commands and controls operations corresponding with said commands,

wherein said memory array comprises a plurality of memory cells and a plurality of word lines,

wherein each of said memory cells stores data as a threshold voltage within a plurality of threshold voltage ranges,

wherein each of said word lines couples to corresponding ones of said memory cells,

wherein said latch circuit is capable of storing data being read out from said memory array or being received with said commands,

wherein said controller is capable of receiving a first address information and first data with a first command included in said commands which indicates a rewriting operation, and

wherein in said rewriting operation, said controller selects one word line according to said first address information, reads data stored in said ones of memory cells coupled to said selected word line to said latch circuit, stores said first data to said latch circuit, erases data stored in all of said ones of memory cells after reading data and before storing data and stores said data stored in said latch circuit to said ones of memory cells.

2. A nonvolatile memory device according to claim 1,

wherein said latch circuit has at least a capacity of storing data read from said ones of memory cells at one time.

3. A nonvolatile memory device according to claim 2,

wherein said controller is capable of receiving a second address information with a second command included in said commands which indicates a read operation, and

wherein in said read operation, said controller selects one word line according to said second address information, reads data stored in said ones of memory cells coupled to said selected word line to said latch circuit and outputs said data from said latch circuit to outside.

4. A nonvolatile memory device according to claim 2,

wherein said controller is capable of receiving a third address information and a second data with a third command included in said commands which indicates a write operation, and

wherein in said write operation, said controller selects one word line according to said second address information, stores said second data to said latch circuit and stores said data from said latch circuit to said ones of memory cells coupled to said selected word line.

5. A nonvolatile memory device according to claim 2,

wherein said controller is capable of receiving a fourth address information with a fourth command included in said commands which indicates an erase operation, and

wherein in said erase operation, said controller selects one word line according to said second address information, erase data stored in said ones of memory cells coupled to said selected word line.

6. A nonvolatile memory device comprising:

a controller;

a latch circuit; and

a memory array,

wherein said controller controls a plurality of operations according to received commands,

wherein said memory array comprises a plurality of memory cells and a plurality of word lines each of which couples to corresponding ones of said memory cells,

wherein each of said memory cells has a threshold voltage within a plurality of threshold voltage distributions, one of which indicates an erase state and another of which indicates a program state,

wherein said controller is capable of receiving a first address information with a first command included in said commands, and

wherein in an operation according to said first command, said controller controls selection of one word line according to said first address information, reading of data stored in said ones of memory cells coupled to said selected one word line to said latch circuit, storing of a first data to said latch circuit, moving of said threshold voltage of said ones of memory cells to within said erase state threshold voltage distribution, and moving of said threshold voltage of said ones of memory cells to within said threshold voltage distribution according to said stored data in said latch circuit.

7. A nonvolatile memory device according to claim 6,

wherein said latch circuit has at least a capacity of storing data read from said ones of memory cells at one time.

8. A nonvolatile memory device according to claim 7,

wherein said controller is capable of receiving a second address information with a second command included in said commands, and

wherein in an operation according to said second command, said controller controls selection of one word line according to said second address information, reading of data stored in said ones of memory cells coupled to said selected word line to said latch circuit, and outputting of said data from said latch circuit to outside.

9. A nonvolatile memory device according to claim 7,

wherein said controller is capable of receiving a third address information and a second data with a third command included in said commands, and

wherein in an operation according to said third command, said controller controls selection of one word line according to said second address information, storing of said second data to said latch circuit, and moving of said threshold voltage of said ones of memory cells coupled to said selected word line to within said threshold voltage distributions according to said stored data in said latch circuit.

10. A nonvolatile memory device according to claim 7,

wherein said controller is capable of receiving a fourth address information with a fourth command included in said commands, and

wherein in an operation according to said fourth command, said controller controls selection of one word line according to said second address information, and moving of said threshold voltage of said ones of memory cells coupled to said selected word line to within said erase state threshold voltage distribution.