Data write circuit

• US 6,567,320 B2
• Filed: 07/01/2002
• Issued: 05/20/2003
• Est. Priority Date: 07/02/2001
• Status: Active Grant

• Current Assignee: Yamaha Corporation
• Original Assignee: Yamaha Corporation
• Inventors: Ando, Tomoaki
• Primary Examiner(s): Lebentritt, Michael S.
• Assistant Examiner(s): Nguyen, Tuan T.
• Application Number:
  US10/186,861
• Publication Number:
  US 20030035323A1
• Time in Patent Office: 323 Days
• Field of Search: 365/189.12, 365/189.01, 365/230.06
• US Class Current: 365/189.12
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A data write circuit is interposed between a CPU and memory, both of which operate based on the same number of bits (e.g., thirty-two bits). The CPU produces address data for designating a specific address in the memory, and access mode designation data for designating one of a byte access mode, half-word access mode, and word access mode. The data write circuit comprises a decoder for decoding the access mode designation data, a logic circuit for generating selection signals, and four selectors, each of which deals with 8-bit data consisting of eight prescribed bits of the original thirty-two bits. Each selector selects either first data read from the memory or second data output from the CPU. Therefore, each selector is capable of selecting the second data, which are substituted for the first data in the memory. Thus, it is possible to perform write operations in desired units in the memory.

Claims

1. A data write circuit for assisting write operations of data between a controller and a memory both of which operate based on the same number of bits, said data write circuit comprising:

a plurality of selectors, each of which has a first input for receiving first data read from the memory in response to address data produced by the controller to designate a specific address for the memory, and a second input for receiving second data output from the controller, so that each selector selectively outputs either the first data or the second data in response to a selection signal; and

a selection signal generator for generating the selection signal based on low-order bits of the address data, and access mode designation data output from the controller.

2. A data write circuit according to claim 1, wherein the controller is a CPU, and the memory is a semiconductor memory.

3. A data write circuit according to claim 1, wherein the memory is constituted as a register.

4. A data write circuit according to claim 2, wherein the memory is constituted as a register.

5. A data write circuit according to claim 1, wherein the memory performs read/write operations in units of thirty-two bits, and each selector selects either the first data consisting of eight bits or the second data consisting of eight bits in response to the selection signal.

6. A data write circuit that is interposed between a memory and a controller for producing address data and access mode designation data, both of which operates based on the same number of bits, said data write circuit comprising:

a decoder for decoding the access mode designation data to designate one of a byte access mode, a half-word access mode, and a word access mode;

a logic circuit for generating a plurality of selection signals based on the output of the decoder and low-order bits of the address data; and

a plurality of selectors, each of which selectively outputs either first data read from the memory in response to the address data, or second data provided from the controller in response to the selection signal.

7. A data write circuit according to claim 6, wherein both the controller and the memory operates based on thirty-two bits, and four sets of the selectors and the selection signals are provided in such a way that each selector selects either the first data consisting of eight prescribed bits or the second data consisting of eight prescribed bits in response to the selection signal.

8. A data write circuit according to claim 7, wherein when the access mode designation data designates the byte access mode, one of the selectors is forced to select the second data, which are substituted for the first data in the memory.

9. A data write circuit according to claim 7, wherein when the access mode designation data designates the half-word access mode, two of the selectors are each forced to select the second data, which are substituted for the first data in the memory.

10. A data write circuit according to claim 7, wherein when the access mode designation data designates the word access mode, all the selectors are each forced to select the second data, which are substituted for the first data.