Fully synchronous pipelined RAM

• US 6,567,338 B1
• Filed: 07/25/2000
• Issued: 05/20/2003
• Est. Priority Date: 04/19/1996
• Status: Expired due to Fees

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Mick, John R.
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Nguyen, Tuan T.
• Application Number:
  US09/625,382
• Time in Patent Office: 1,029 Days
• Field of Search: 365/233, 365/191, 365/189.07
• US Class Current: 365/189.14
• CPC Class Codes: G11C 2207/2218 Late write
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into the memory during subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. Thus, no “bus turnaround” down time is experienced by the system thereby increasing the bandwidth of the system. The system can operate in a single pipeline mode or a dual pipeline mode.

Claims

1. memory device comprising:

a memory array;

a controller, coupled to the memory array, including pipeline circuitry for storing a sequence of at least three pending memory operations, wherein the at least three pending memory operations can include any sequence of read and write operations;

wherein the pipeline circuitry includes read operation processing circuitry that, when the pipeline circuitry stores a read operation and a write operation having identical addresses, and the read operation is later in the sequence than the write operation, processes the read operation by accessing data stored in the pipeline circuitry for the write operation instead of accessing data in the memory array.

2. The memory device of claim 1, wherein the memory device performs write and read operations without an idle cycle between the read operation and the write operation when switching from the read operation to the write operation and when switching from the write operation to the read operation.

3. The device of claim 2 wherein the controller comprises:

a first address register;

a second address register coupled to the first address register;

a third address register coupled to the second address register;

a memory array;

a first data register coupled to the memory array;

a second data register coupled to the first data register;

a first comparator coupled to the first, second and third address registers;

a second comparator coupled to the first, second and third address registers.

4. The device of claim 1 wherein the controller has storage circuitry for storing two pending write operations.

5. The device of claim 3 wherein the controller further comprises:

pipeline circuitry for performing a read operation while storing the two pending write operations;

pipeline circuitry for performing a write operation while storing the two pending write operations.

6. The device of claim 5 wherein the memory device is an SRAM.

7. The device of claim 6, wherein the SRAM performs write and read operations without an idle cycle between the read operation and the write operation when switching from the read operation to the write operation and when switching from the write operation to the read operation.

8. The device of claim 7 wherein the controller comprises:

a first address register;

a second address register coupled to the first address register;

a third address register coupled to the second address register;

a memory array;

a first data register coupled to the memory array;

a second data register coupled to the first data register;

a first comparator coupled to the first, second and third a memory array;

a second comparator coupled to the first, second and third address registers.

9. A method of controlling a memory device comprising:

storing a sequence of at least three pending memory operations in a pipeline, the sequence of pending memory operations including a read operation and a write operation having identical addresses, wherein the read operation is later in the sequence than the write operation; and

processing the read operation by accessing data stored in the pipeline for the write operation instead of accessing data in a memory array.