Apparatus and method for determining a synchronization signal

• US 6,567,424 B1
• Filed: 11/17/1997
• Issued: 05/20/2003
• Est. Priority Date: 08/07/1995
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Girardeau, James W. Jr.
• Primary Examiner(s): Yao, Kwang Bin
• Application Number:
  US08/971,257
• Time in Patent Office: 2,010 Days
• Field of Search: 370/503, 370/509, 370/510, 370/512, 370/513, 370/514, 370/520, 375/360, 375/365, 375/368, 714/775, 714/798
• US Class Current: 370/509
• CPC Class Codes: H04J 3/0608 Detectors therefor, e.g. correlators, state machines
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/4381 Recovering the multiplex stream from a specific network, e.g. recovering MPEG packets from ATM cells transmission of MPEG streams over ATM H04L12/5601
• CPC Class Codes: H04N 21/4788 communicating with other users, e.g. chatting arrangements for providing for computer conferences, e.g. chat rooms, to substation in data switching networks H04L12/1813; distributed application using peer-to-peer [P2P] networks H04L67/104
• CPC Class Codes: H04N 5/04 Synchronising for television systems using pulse code modulation H04N7/56
• CPC Class Codes: H04N 5/08 Separation of synchronising signals from picture signals
• CPC Class Codes: H04N 7/147 Communication arrangements, e.g. identifying the communication as a video-communication, intermediate storage of the signals selecting H04Q
• CPC Class Codes: H04N 7/148 Interfacing a video terminal to a particular transmission medium, e.g. ISDN

Abstract

The present invention relates to circuitry and an associated method for detecting a synchronization signal in a multi-media data transmission system. Preferably, the circuitry (10) includes process controller (40), memory (44), and a comparator (46). The process controller (40) controls the receipt of bit groups of data (52) and the storage of the bit groups of data (50) in the memory (44). The memory (44) operably couples to the process controller (40), receives the data, and stores the data in a predetermined order based upon the process controller (40). The comparator (46) couples to the process controller (40) and the memory (44) and compares the corresponding index locations of the bit groups (52) to a synchronization pattern (58). When the synchronization pattern (58) matches the predetermined set of bit groups (52), the comparator (46) generates the synchronization detection signal (60). The synchronization detection signal (60) then allows further equipment within the receiver to selectively operate on the data blocks received.

Claims

1. A method for detecting a synchronization signal in a multi-media data transmission, the method comprising the steps of

receiving a plurality of bit groups, wherein the plurality of bit groups represents at least a portion of the multi-media data transmission;

storing the plurality of bit groups into a memory based on a predetermined storage technique, wherein each stored bit group within the plurality of bit groups has a plurality of index locations;

retrieving at least a first set of bit groups of the plurality of bit groups from predetermined locations of the memory; and

monitoring the plurality of index locations of each of the first set of bit groups for the synchronization signal.

2. The method of claim 1 wherein the step retrieving at least a first set of bit groups further comprises retrieving a second set of bit groups of the plurality of bit groups from second predetermined locations in the memory.

3. The method of claim 2 wherein the step retrieving at least a first set of bit groups further comprises retrieving a third set of bit groups of the plurality of bit groups from third predetermined locations in the memory.

4. The method of claim 3 wherein the step monitoring the plurality of index locations further comprises comparing the plurality of index locations of the first set of bit groups, the second set of bit groups, and the third set of bit groups with a known synchronization pattern.

5. The method of claim 1 wherein the step receiving a plurality of bit groups further comprises receiving a plurality of bytes, each corresponding to one of the plurality of bit groups, and the step of storing further comprises storing the bytes into a memory based on a predetermined storage technique, wherein each stored byte within the plurality of bytes has a plurality of index locations, each index location is associated with a specific bit location within the byte.

6. The method of claim 5 wherein the step of scanning index locations further comprises scanning one bit location of each of the plurality of bytes in the first set of bit groups for the synchronization signal.

7. A multi-media synchronization detection circuit comprising:

a process controller;

a memory operably coupled to the process controller, wherein the process controller provides a control signal to the memory, for instructing the memory to store a multi-media transmission in a predetermined order, and the memory stores the multi-media transmission as a plurality of bit groups, wherein there is a plurality of index locations associated with each bit group within the plurality of bit groups, wherein each one of the plurality of index locations references a portion of the stored multi-media transmission; and

a comparator operably coupled to the process controller and the memory, wherein the comparator performs a comparison between each of the portions of the multi-media transmission referenced by one of the plurality of index locations and a synchronization pattern, and the comparator for generating a synchronization detection signal when the portion of the multi-media transmission matches the synchronization pattern.

8. The multi-media synchronization detection circuit of claim 7 wherein the comparator further comprises a state machine that performs the comparison of the corresponding index locations of the plurality of bit groups with the synchronization pattern.

9. The multi-media synchronization detection circuit of claim 8 wherein the state machine further comprises a plurality of index state machines, each index state machine performs a comparison of a particular index location of the plurality of bit groups with the synchronization pattern.

10. The multi-media synchronization detection circuit of claim 7 wherein each bit group comprises a byte.

11. The multi-media synchronization detection circuit of claim 10 wherein each corresponding index location is a bit location of a byte.

12. A multi-media synchronization detection circuit comprising:

an address generation unit;

a circular buffer operably coupled to the address generation unit, wherein the address generation unit provides a control signal to the circular buffer, wherein the control signal instructs the circular buffer to store a multi-media transmission in a predetermined order, wherein the circular buffer stores the multi-media transmission as a plurality of bit groups, and wherein each bit group is stored as a row of data in the circular buffer; and

a synchronization detector operably coupled to the address generation unit and the circular buffer, wherein the synchronization detector compares bit columns of a predetermined set of bit groups of the plurality of bit groups with a synchronization pattern, and wherein the synchronization detector generates a synchronization detection signal when one of the bit columns of the predetermined set of bit groups substantially matches the synchronization pattern.

13. A method for detecting a synchronization signal in a multi-media data transmission, the method comprising the steps of:

receiving a plurality of bit groups, wherein the plurality of bit groups represents at least a portion of the multi-media data transmission;

storing the plurality of bit groups into a memory based on a predetermined storage technique, wherein each bit group of the plurality of bit groups is stored as a row of data in the memory to form a column of bit groups having a first index referencing all bits associated with a first row location, and a second index referencing all bits associated with a second row location;

retrieving at least a first set of bit groups of the plurality of bit groups from predetermined locations of the memory; and

scanning a data referenced by the first index and data referenced by the second index to determine if a synchronization signal is referenced by the first of the second data.