Preemptive timer multiplexed shared memory access

• US 6,567,426 B1
• Filed: 03/05/1998
• Issued: 05/20/2003
• Est. Priority Date: 03/05/1998
• Status: Expired due to Term

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Silicon Graphics Incorporated (Graphics Properties Holdings, Inc.)
• Inventors: van Hook, Timothy J., Ezer, Gulbin
• Primary Examiner(s): Olms, Douglas
• Assistant Examiner(s): Sam, Phirin
• Application Number:
  US09/035,687
• Time in Patent Office: 1,902 Days
• Field of Search: 370/535, 370/401, 370/402, 370/412, 370/419, 370/413, 370/415, 370/462, 370/404, 370/421, 370/423, 370/424, 370/438, 370/451, 370/458, 370/459, 711/100, 711/105, 711/109, 711/145, 711/147, 711/169, 714/9, 714/10, 710/22, 710/23, 710/124
• US Class Current: 370/535
• CPC Class Codes: G06F 13/1663 Access to shared memory

Abstract

The present invention is directed to a method and system for sharing a data memory among a plurality of processors in a computer system. In the system and method of the present invention, a plurality of processors are coupled to a data memory for accessing the data memory in N-bit bandwidth. The present invention receives an active signal for accessing the data memory from the plurality of processors. A processor requesting accessing to the data memory asserts an active signal. Among the processors asserting active signals, a processor is selected as a memory master to the data memory. The present invention then transfers the N-bit wide data between the selected processor and the data memory in a time slot defined by a clock cycle. Only one processor is allowed access to the data memory during a given time slot. In the preferred embodiment of the present invention, the N-bit bandwidth is large enough to accommodate the data requirements of all the processors.

Claims

1. In a computer system, a method for sharing access to a data memory among processors comprising, the steps of:

receiving an active signal for accessing the data memory from a plurality of processors, one active signal per processor, wherein the data memory is accessible to the processor for transferring an N-bit wide data to or from the data memory;

selecting a processor as a memory master among the processors asserting the active signals to the data memory;

the processors further including;

a signal processor;

a plurality of co-processors, wherein the co-processors include a direct memory access (DMA) processor;

selecting the DMA processor as a bus master if the DMA processor is active;

selecting a co-processor as the bus master from the plurality of co-processors if the DMA processor is not active;

selecting the signal processor as the bus master if neither the DMA processor nor any of the co-processors is active; and

transferring the N-bit wide data between the selected processor and the data memory in a time slot defined by a clock;

the transferring step further comprises the steps of;

a) loading the N-bit wide data into an N-bit wide register;

b) reading, by the selected processor, a subset of N-bit wide data during the clock cycle through a multiplexer until all N-bits have been read from the register over a plurality of clock cycles.

2. The method as recited in claim 1, wherein the transferring step further comprises the steps of:

transferring a subset of the N-bit wide data into the N-bit wide register in a clock cycle until all N-bits have been loaded into the register over a plurality of the clock cycles; and

writing the N-bit wide data in the register into the data memory.

3. The method as recited in claim 1, wherein the selecting step further comprises the steps of:

selecting a co-processor as the bus master from the plurality of co-processors; and

selecting the signal processor as the bus master if none of the co-processors are active.

4. The method as recited in claim 1, wherein the co-processors include a graphics processor, a bit stream processor, a quantization processor for performing quantization and discrete cosine transform, and a floating point processor.

5. The method as recited in claim 4, wherein the co-processors further include a motion compensation processor sharing a read access to the data memory with the graphics processor.

6. The method as recited in claim 5, wherein N is 128.

7. The method as recited in claim 6, wherein the time slot is generated by a state machine counter.

8. The method as recited in claim 7, wherein the state machine counter repeatedly generates a cycle of M states, from 0 to M−

1, one state for each time slot.

9. The method as recited in claim 8, wherein M is 8.

10. The method as recited in claim 9, wherein the 8 states define a bus master selection pattern wherein:

the state 0 is assigned to the DMA processor;

the state 1 is assigned to the graphics processor for reading from the data memory;

the state 2 is assigned to the bit stream processor for reading from the data memory;

the state 3 is assigned to the bit stream processor for writing to the data memory;

the state 4 is assigned to the DMA processor for transferring data to and from the data memory and to the quantization processor for writing to the data memory, wherein the DMA processor preempts the quantization processor;

the state 5 is assigned to the graphics processor for reading from the data memory and to the quantization processor for writing to the data memory, wherein the graphics processor preempts the quantization unit;

the state 6 is assigned to the quantization processor for performing discrete cosine transformation for reading from the data memory; and

the state 7 is assigned to the quantization processor for performing quantization for reading from the data memory.

11. The method as recited in claim 9, wherein the 8 states define a bus master selection pattern wherein:

the state 0 is assigned to the graphics processor for reading from the data memory;

the state 1 is assigned to the DMA processor for transferring the data to and from the data memory;

the state 2 is assigned to the bit stream processor for reading from the data memory;

the state 3 is assigned to the bit stream processor for writing to the data memory;

the state 4 is assigned to the graphics processor for reading from the data memory and to the quantization processor for writing to the data memory, wherein the graphics processor preempts the quantization unit;

the state 5 is assigned to the DMA processor for transferring data to and from the data memory and to the quantization processor for writing to the data memory, wherein the DMA processor preempts the quantization processor;

the state 6 is assigned to the quantization processor for performing discrete cosine transformation for reading from the data memory; and

the state 7 is assigned to the quantization processor for performing quantization for reading from the data memory.

12. The method as recited in claim 9, wherein the 8 states define a bus master selection pattern wherein:

the state 0 is assigned to the graphics processor for reading from the data memory;

the state 1 is assigned to the bit stream processor for reading from the data memory;

the state 2 is assigned to the DMA processor for transferring the data to and from the data memory;

the state 3 is assigned to the bit stream processor for writing to the data memory;

the state 4 is assigned to the graphics processor for reading from the data memory and to the quantization processor for writing to the data memory, wherein the graphics processor preempts the quantization unit;

the state 5 is assigned to the quantization processor for performing discrete cosine transformation for reading from the data memory;

the state 6 is assigned to the DMA processor for transferring data to and from the data memory and to the quantization processor for writing to the data memory, wherein the DMA processor preempts the quantization processor; and

the state 7 is assigned to the quantization processor for performing quantization for reading from the data memory.

13. A computer system with a shared data memory among processors, comprising:

a data memory accessible during a time slot defined by a clock cycle;

a plurality of processors coupled to the data memory, a processor accessing the data memory in an N-bit data word;

wherein the processors comprise;

a) a direct memory access (DMA) processor coupled between a memory controller and a main memory, the DMA processor transferring data between the main memory and the data memory during an active state;

b) a co-processor coupled to the memory controller, said co-processor accessing the data memory when the DMA processor is not active;

c) a signal processor coupled to the memory controller, a programmable processor accessing the data memory when all other processors are idle;

the memory controller, coupled between the data memory and the data processors, for interfacing the processors and the data memory, wherein the memory controller selects a processor among the plurality of processors to have exclusive access to the data memory during the time slot according to an arbitration pattern and transfers a specified N-bit data word between the data memory and the selected processor during the time slot, said memory controller coupled to the main memory;

an interface circuit comprising a) a plurality of N-bit registers for holding the N-bit data words for transfer between the processors and the data memory, at least one register for each processor;

b) a plurality of multiplexers for transferring a subset of the N-bit data word in one clock cycle until all the data bits in the N-bits data word has been transferred, said multiplexers coupled to the N-bit registers, one multiplexer for each register.

14. The system as recited in claim 13, wherein the memory controller further comprises:

an interface circuit for interfacing data transfers between the processors and the data memory; and

a controller circuit coupled to the interface circuit for arbitrating access among the processors to the data memory during the time slot.

15. The system as recited in claim 14, wherein N is 128.

16. The system as recited in claim 15, wherein the co-processor further includes a graphics processor, a bit stream processor, a quantization processor, a motion compensation processor, and a floating point processor.

17. The system as recited in claim 16, wherein the motion compensation processor and the graphics processor further share access to the data memory.

18. The system as recited in claim 17, wherein the memory controller generates the time slot using a state machine counter.

19. The system as recited in claim 18, wherein the memory controller generates a plurality of cycles comprised of M states, from 0 to M−

1, one state for each time slot and M states per cycle.

20. The system as recited in claim 19, wherein M is 8.

21. The system as recited in claim 20, wherein the 8 states define the arbitration pattern wherein:

the state 0 is assigned to the DMA processor;

the state 1 is assigned to the graphics processor for reading from the data memory;

the state 2 is assigned to the bit stream processor for reading from the data memory;

the state 3 is assigned to the bit stream processor for writing to the data memory;

the state 4 is assigned to the DMA processor for transferring data to and from the data memory and to the quantization processor for writing to the data memory, wherein the DMA processor preempts the quantization processor;

the state 5 is assigned to the graphics processor for reading from the data memory and to the quantization processor for writing to the data memory, wherein the graphics processor preempts the quantization unit;

the state 6 is assigned to the quantization processor for performing discrete cosine transformation for reading from the data memory; and

the state 7 is assigned to the quantization processor for performing quantization for reading from the data memory.

22. The system as recited in claim 20, wherein the 8 states define an arbitration pattern wherein:

the state 0 is assigned to the graphics processor for reading from the data memory;

the state 1 is assigned to the DMA processor for transferring the data to and from the data memory;

the state 2 is assigned to the bit stream processor for reading from the data memory;

the state 3 is assigned to the bit stream processor for writing to the data memory;

the state 4 is assigned to the graphics processor for reading from the data memory and to the quantization processor for writing to the data memory, wherein the graphics processor preempts the quantization unit;

the state 5 is assigned to the DMA processor for transferring data to and from the data memory and to the quantization processor for writing to the data memory, wherein the DMA processor preempts the quantization processor;

the state 6 is assigned to the quantization processor for performing discrete cosine transformation for reading from the data memory; and

the state 7 is assigned to the quantization processor for performing quantization for reading from the data memory.

23. The system as recited in claim 20, wherein the 8 states define an arbitration pattern wherein:

the state 0 is assigned to the graphics processor for reading from the data memory;

the state 1 is assigned to the bit stream processor for reading from the data memory;

the state 2 is assigned to the DMA processor for transferring the data to and from the data memory;

the state 3 is assigned to the bit stream processor for writing to the data memory;

the state 4 is assigned to the graphics processor for reading from the data memory and to the quantization processor for writing to the data memory, wherein the graphics processor preempts the quantization unit;

the state 5 is assigned to the quantization processor for performing discrete cosine transformation for reading from the data memory;

the state 6 is assigned to the DMA processor for transferring data to and from the data memory and to the quantization processor for writing to the data memory, wherein the DMA processor preempts the quantization processor; and

the state 7 is assigned to the quantization processor for performing quantization for reading from the data memory.