Method and circuitry for acquiring a signal in a read channel

• US 6,567,489 B1
• Filed: 02/08/1999
• Issued: 05/20/2003
• Est. Priority Date: 02/08/1999
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Glover, Kerry C.
• Primary Examiner(s): Bocure, Tesfaldet
• Application Number:
  US09/246,408
• Time in Patent Office: 1,562 Days
• Field of Search: 375/372, 375/376, 375/345, 375/355, 375/362-366, 375/369, 375/229, 360/51, 360/39, 369/59.1, 369/59.19
• US Class Current: 375/376
• CPC Class Codes: G11B 20/10009 Improvement or modification of read or write signals
• CPC Class Codes: G11B 20/1426 conversion to or from block codes or representations thereof
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H04L 7/10 Arrangements for initial synchronisation

Abstract

A method for acquiring a signal in a read channel (18), the read channel (18) having an equalizer (48), includes performing an automatic gain control sequence; performing a phase locked loop sequence that includes performing a fast phase locked loop step, the fast phase locked loop step including bypassing the equalizer; and performing a synchronization search sequence.

Claims

1. A method for acquiring a signal in a read channel, the read channel having an equalizer, the method comprising the steps of:

performing an automatic gain control sequence;

performing a phase locked loop sequence that includes performing a fast phase locked loop step, the fast phase locked loop step including bypassing the equalizer; and

performing a synchronization search sequence.

2. The method of claim 1, wherein performing a phase locked loop sequence further includes performing a slow phase locked loop step.

3. The method of claim 1, wherein bypassing the equalizer comprises bypassing an analog finite impulse response filter.

4. The method of claim 1, wherein performing an automatic gain control sequence includes:

setting and holding the gain applied to the signal;

performing a fast continuous automatic gain control step; and

performing a slow continuous automatic gain control step.

5. The method of claim 1, wherein the signal includes a preamble section.

6. The method of claim 1, wherein performing a phase locked loop sequence includes:

synchronizing to a crystal clock;

performing a zero phase restart to the signal; and

performing a slow phase locked loop step after performing a test phase locked loop step.

7. A method for acquiring a signal in a read channel, the method comprising the steps of:

performing an automatic gain control sequence, the automatic gain control sequence including performing a continuous automatic control step and a sampled automatic gain control step;

performing a phase locked loop sequence; and

performing a synchronization search sequence.

8. The method of claim 7, wherein performing a phase locked loop sequence includes:

synchronizing to a crystal clock;

performing a zero phase restart to the signal; and

performing a slow phase locked loop step after the performing a fast phase locked loop step.

9. The method of claim 7, wherein performing a phase locked loop sequence includes performing a test phase locked loop step that includes bypassing an equalizer in the read channel.

10. The method of claim 9, wherein the equalizer is an analog finite impulse response filter.

11. The method of claim 7, wherein the signal includes a preamble section.

12. A method for acquiring a signal in a read channel comprising the steps of:

performing an automatic gain control sequence;

performing a phase locked loop sequence, the phase locked loop sequence including performing a zero phase restart to the signal;

performing a synchronization search sequence,

wherein using an equalizer in the read channel includes using a finite impulse response equalizer,

wherein performing a phase locked loop sequence further comprises;

synchronizing to a crystal clock; and

performing a slow phase locked loop step after performing a fast phase locked loop step.

13. A method for acquiring a signal in a read channel comprising the steps of:

performing an automatic gain control sequence;

performing a phase locked loop sequence, the phase locked loop sequence including performing a zero phase restart to the signal;

performing a synchronization search sequence,

wherein using an equalizer in the read channel includes using a finite impulse response equalizer, wherein;

performing an automatic gain control sequence that includes the steps of;

setting and holding the gain applied to the signal;

performing a fast continuous automatic gain control step;

performing a slow continuous automatic gain control step;

performing a sampled automatic gain control step;

performing a synchronization search sequence that includes the steps of;

performing a wait step;

performing a search step; and

performing a found step.

14. A read channel, including circuitry for acquiring a signal in a read channel, comprising:

a sequence controller operable to generate an automatic gain control fast/slow enable signal;

an automatic gain control circuit operable to generate an output gain signal, the automatic gain control circuit responsive to the automatic gain control fast/slow enable signal to perform either a fast continuous automatic gain control step or a slow continuous automatic gain control step;

a variable gain amplifier responsive to the output gain signal and operable to amplify an analog read signal by an amount related to the output gain signal to generate an amplified analog read signal;

a continuous-time filter operable to filter the amplified analog read signal to generate a filtered read signal;

an equalizer;

a selection circuit;

a sampler operable to sample the filtered read signal in response to receiving a read clock signal and operable to generate and selectively provide a discrete, analog read signal to either the equalizer or to the selection circuit;

the equalizer selectively operable to filter the discrete analog read signal to generate a discrete, equalized read signal;

the selection circuit operable to provide either the discrete analog read signal or the discrete, equalized read signal as a reference signal;

a phase locked loop circuit operable to receive a clock signal and the reference signal and to generate the read clock signal in response; and

a detector operable to analyze the discrete, equalized read signal to generate a digital data output signal.

15. The read channel of claim 14, wherein the sequence controller is further operable to generate a bypass enable signal and the selection circuit is responsive to the bypass enable signal to provide the discrete, analog read signal as the reference signal.

16. The read channel of claim 14, wherein the sequence controller includes a plurality of state machines.

17. The read channel of claim 14, wherein the sequence controller is further operable to receive at least one input signal to control generation of the automatic gain control fast/slow enable signal.