Thread switch control in a multithreaded processor system

• US 6,567,839 B1
• Filed: 10/23/1997
• Issued: 05/20/2003
• Est. Priority Date: 10/23/1997
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Levenstein, Sheldon Bernard, Eickemeyer, Richard James, Wottreng, Andrew Henry, Borkenhagen, John Michael, Flynn, William Thomas
• Primary Examiner(s): Banankhah, Majid A.
• Application Number:
  US08/957,002
• Time in Patent Office: 2,035 Days
• Field of Search: 709/102, 709/103, 709/100, 709/101, 709/104, 709/107, 709/108, 712/228, 712/23, 712/205, 712/220, 712/43, 714/47
• US Class Current: 718/103
• CPC Class Codes: G06F 9/3009 Thread control instructions
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system

Abstract

A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread switch can occur. Upon the occurrence of a thread switch event, the state and priority of all threads are dynamically interrogated to determine which thread should be the active thread executing the processor. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive unproductive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a thread switch manager capable of changing the priority of the different threads and thus superseding thread switch events.

Claims

1. A method of computer processing, comprising:

(a) storing a first state of at least one active thread in at least one hardware register integrated with a multithreaded processor in a processor core;

(b) executing the at least one active thread in the multithreaded processor;

(c) changing the first state of the at least one active thread;

(d) storing a second state of at least one background thread in the at least one hardware register in the multithreaded processor;

(e) determining in a hardware thread switch logic unit integrated with the multithreaded processor in the processor core if changing the first state of the at least one active thread causes the multithreaded processor to switch execution to the at least one background thread.

2. The method of claim 1, wherein the step of changing the first state of the at least one active thread comprises describing an active thread latency event which stalls execution of the multithreaded processor.

3. The method of claim 1, wherein the step of changing the first state of the at least one active thread comprises changing priority of the active thread.

4. The method of claim 1, further comprising:

(f) switching execution to the at least one background thread.

5. The method of claim 4, further comprising:

(g) counting the number of processor cycles in the hardware thread switch logic unit that the at least one active thread has been executing and when the number of execution cycles is equal to a time-out value, then switching execution to the at least one background thread.

6. The method of claim 4, further comprising:

(g) receiving an external interrupt signal and then switching execution to the at least one background thread.

7. The method of claim 4, wherein the step of determining if changing the first state of the at least one active thread causes the multithreaded processor to switch execution to the at least one background thread further comprises:

(g) checking if the change of the first state results from an active thread latency event;

(h) determining if the latency event is a thread switch event; and

(i) determining if the thread switch event is enabled.

8. The method of claim 7, wherein the thread switch event is enabled when at least one bit in a thread switch control register in the hardware thread switch logic unit corresponding to the thread switch event is enabled.

9. The method of claim 4, wherein the step of determining if changing the first state of the at least one active thread causes the multithreaded processor to switch execution to the at least one background thread, further comprises:

(g) changing priority of the at least one active thread to be equal to or lower than priority of the at least one background thread.

10. The method of claim 1, further comprising:

(f) changing priority of the at least one background thread to be equal to or higher than priority of the at least one active thread, and

(g) determining if changing the second state of the at least one background thread causes the multithreaded processor to switch execution to the of at least one background thread.

11. The method of claim 10, further comprising:

(h) switching execution to the at least one background thread.

12. The method of claim 10, further comprising:

(h) not switching execution to the at least one background thread.

13. The method of claim 1, further comprising:

(f) not switching execution to the at least one background thread.

14. The method of claim 13, wherein the step of determining if changing the first state of the at least one active thread causes the multithreaded processor to switch execution to the at least one background thread further comprises:

(g) checking if the change of the first state results from a latency event;

(h) determining if the latency event is a thread switch event; and

(i) determining that the thread switch event is not enabled in a hardware register in the thread switch logic unit.

15. The method of claim 13, further comprising:

(g) counting a number of thread switches that has occurred away from the at least one active thread in the hardware thread switch logic unit;

(h) comparing the number with a count threshold stored in a register in the hardware thread switch logic unit;

(i) signaling when the number is equal to the count threshold and in response thereto not switching execution.

16. The method of claim 2, wherein the step of determining if changing the first state of the at least one active thread causes the multithreaded processor to switch execution to the at least one background thread further comprises:

comparing the first state of the active thread with a second state of at least one background thread; and

selecting as determined by the hardware thread switch logic unit the thread having the latency event of lowest expected duration for execution in the multithreaded processor.

17. The method of claim 16, further comprising:

(f) switching execution to the at least one background thread when the second state is ready or the background thread is awaiting a background latency event of equal or shorter expected duration than the active thread latency event.

18. The method of claim 17, wherein the active thread latency event is an L2 cache miss or a table lookaside buffer miss and the background latency event is a L1 cache miss, said L2 cache miss, said table lookaside buffer miss, and said L1 cache miss represented by bits in a register of said hardware thread switch logic.

19. The method of claim 16, further comprising:

(f) changing the second state of the at least one background thread;

(g) switching execution to the at least one background thread when the active thread latency event is of longer expected duration than a background latency event or when the second state of the at least one background thread is ready.

20. A method of computer processing, comprising:

(a) storing a first state of at least one active thread in at least one hardware register in hardware thread switch logic unit integrated with a multithread processor in a processor core;

(b) storing a second state of at least one background thread in the at least one hardware register in the hardware thread switch logic unit;

(c) executing the at least one active thread in a multithreaded processor;

(d) changing the first state of the at least one active thread if any one of the following conditions occur;

(i) execution of the at least one active thread stalls because of a latency event represented by entries in a register in the hardware thread switch logic unit;

(ii) altering priority of the at least one active thread to be equal to or lower than priority of the at least one background thread;

(e) determining in the hardware thread switch logic unit if changing the first state of the at least one active thread causes the multithreaded processor to switch execution to the at least one background thread by;

(i) determining if the latency event is a thread switch event; and

(ii) determining if the thread switch event is enabled in a register in the hardware thread switch logic unit;

(f) switching execution to the at least one background thread under one of the following conditions;

(i) counting the number of processor cycles that the at least one active thread has been executing and when the number of execution cycles is equal to a time-out value, then switching execution to the at least one background thread;

(ii) receiving an external interrupt signal and then switching execution to the at least one background thread;

(iii) at least one bit in a thread switch control register in the hardware thread switch logic unit corresponding to the thread switch event is enabled;

(iv) changing priority of the at least one background thread to a priority equal to or higher than the priority of the at least one active thread;

(g) not switching execution to the at least one background thread under one of the following conditions;

(i) determining the latency event is not a thread switch event;

(ii) determining that the thread switch event is not enabled in the hardware thread switch logic unit;

(iii) counting in the hardware thread switch logic unit a number of thread switches that has occurred away from the at least one active thread, then comparing the number with a count threshold and signaling the thread switch control register when the number is equal to the count threshold.

21. A hardware thread state register in a hardware thread switch logic unit integrated with a multithread processor in a processor core, the hardware thread switch logic unit comprising a plurality of bits to store a state of at least one active thread and a state of at least one background thread, the state indicating at least whether or not the threads have experienced a cache miss.

22. The thread state register of claim 21, wherein some of the plurality of bits further indicate:

(a) a latency event other than a cache miss,

(b) if a transition to each respective state results in switching execution to another of the threads, and

(c) priority of the threads.

23. A data processing system, comprising:

(a) a central processing unit comprising a multithreaded processor capable of executing at least one active thread, a hardware thread switch logic unit having at least one register capable of storing the state of at least one active thread and at least one background thread, a plurality of execution units, a plurality of registers, a hardware storage control unit, and an instruction unit;

wherein the execution units, the registers, the hardware thread switch logic unit, the hardware storage control unit, and the instruction unit are integrated with the multithreaded processor in the central processing unit;

(b) a plurality of cache memories connected intermediate between said central processing unit and a main memory;

(c) a plurality of external connections comprising a bus interface, a bus, at least one input/output processor connected to at least one of the following;

a tape drive, a data storage device, a computer network, a fiber optics communication, a workstation, a peripheral device, an information network;

any of which are capable of transmitting data and instructions to the central processing unit over the bus;

wherein when the at least one active thread stalls execution, the event and reason thereof are communicated to the hardware storage control unit, the hardware storage control unit sends a corresponding signal to the hardware thread switch logic unit, and the hardware thread switch logic unit changes the state of the at least one active thread in said at least one register and determines if the multithreaded processor will switch threads and execute one of said at least one background thread.

24. A computer processing system comprising:

(a) an integrated multithreaded processor in a central processing unit;

(b) a thread switch logic unit having at least one hardware thread state register and a hardware thread switch control register in the central processing unit integrated with the multithreaded processor; and

(c) a hardware storage control unit in the central processing unit integrated with the multithreaded processor and the thread switch logic unit

wherein the hardware storage control unit receives data, instructions, and input for the multithreaded processor and signals the thread switch logic unit and the multithreaded processor according to the data, instructions, and input, and in response thereto the thread switch logic unit outputs signals to the multithreaded processor.

25. The computer processing system of claim 24, further comprising:

(a) at least one data cache external to the central processing unit;

(b) at least one memory external to the central processing unit;

(c) at least one instruction unit integrated within the central processing unit; and

(d) at least one execution unit integrated within the central processing unit.

26. The computer processing system of claim 25, wherein the hardware storage control unit further comprises:

(a) a transition cache;

(b) at least a first multiplexer connected to the at least one instruction unit in the central processing unit to supply instructions for execution to the multithreaded processor;

(c) at least a second multiplexer to supply data to the at least one execution unit.

27. The computer processing system of claim 25, wherein the thread switch logic unit further comprises:

(a) a hardware thread state register; and

(b) a hardware thread switch control register.

28. The computer processing system of claim 25, wherein the thread switch logic unit further comprises:

(c) a hardware forward progress count register;

(d) a hardware thread switch time-out register; and

(e) a thread switch manager.

29. A computer processing system comprising:

a central processing unit having a plurality of integrated circuits connected together configured as at least one multithreaded processor capable of executing at least one active thread and storing at least one background thread of a plurality of threads of instructions, at least one execution unit wherein the data and instructions are executed;

a hardware storage control unit comprising a transition cache, at least a first multiplexer to transmit instructions from the transition cache or an instruction cache or a memory to an instruction unit, and at least a second multiplexer to transmit data from at least one data cache or the transition cache or a memory to the at least one execution unit, at least one sequencer unit to provide control signals to at least the memory, the caches, the multiplexers, and the execution units;

a thread switch logic unit comprising a hardware thread state register to store states of the at least one active and background thread, and a hardware thread switch control register having bits to enable a plurality of thread switch events, the thread switch logic unit also receiving and transmitting control signals from and to the sequencer unit, and

a plurality of cache memories including the at least one data cache and the instruction cache,

wherein the thread switch logic unit receives signals from the hardware storage control unit characterizing the state of the plurality of threads in the multithreaded processor and in response thereto, determines whether to switch execution from the at least one active thread in the multithreaded processor.

30. A computer processor system, comprising:

(a) means to process at least one active thread of instructions integrated in a hardware multithreaded central processing unit;

(b) means to store a state of the at least one active thread in a hardware register integrated in the multithreaded central processing unit;

(c) means to store a state of at least one background thread of instructions in a hardware register integrated in the multithreaded central processing unit;

(d) means to change the states of the at least one active thread and the at least one background thread in the hardware registers,

(e) means, responsive to the means to change the states, to switch threads so that the processing means processes the at least one background thread.

31. The computer processor system of claim 30, wherein the means to change the states of the at least one active thread and the at least one background thread comprises:

(a) an external hardware interrupt signal;

(b) a thread switch manager; and

(c) hardware means integrated in the multithreaded central processing unit to signal one of a plurality a latency events experienced by the processing means which stall the processing means from continued processing of the at least one active thread.

32. The computer processor system of claim 30, wherein the means to switch threads comprises:

(a) hardware means integrated in the multithreaded central processing unit to enable one of a plurality of latency events to be a thread switch event;

(b) means to change priority of any of the threads;

(c) hardware means integrated in the multithreaded central processing unit to time-out the means to process;

(d) hardware means integrated in the multithreaded central processing unit to compare the states of each thread and select the thread having one of a plurality of latency events with the lowest expected latency.

33. The computer processor system of claim 30, further comprising means to disregard the means to switch threads.

34. A computer processor, comprising:

a multithreaded processor capable of executing at least one of a plurality of threads of instructions in a central processing unit;

a first plurality of hardware registers integrated with the multithreaded processor in the central processing unit, the first plurality of hardware registers having a plurality of bits to indicate the states of each of the plurality of threads of instructions;

a second plurality of hardware registers integrated with the multithreaded processor in the central processing unit, the second plurality of hardware registers having a plurality of bits to indicate a plurality of first events upon which the multithreaded processor will switch execution of threads;

wherein the computer processing system can switch threads if a second event which changes the states of any of the plurality of threads of instructions in the first plurality of hardware registers is enabled in the second plurality of hardware registers.